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參數(shù)資料
| 型號(hào)： | BS62LV2001STI |
| 廠商： | BRILLIANCE SEMICONDUCTOR, INC. |
| 英文描述： | Very Low Power/Voltage CMOS SRAM 256K X 8 bit |
| 中文描述： | 非常低功率/電壓CMOS SRAM的256K × 8位 |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大?。?/td> | 283K |
| 代理商： | BS62LV2001STI |
R0201-BS62LV2001
Revision 2.5
April 2002
1
PIN CONFIGURATIONS
A17
Very Low Power/Voltage CMOS SRAM
256K X 8 bit
Wide Vcc operation voltage : 2.4V ~ 5.5V
Very low power consumption :
Vcc = 3.0V
C-grade : 20mA (Max.) operating current
I- grade : 25mA (Max.) operating current
0.1uA (Typ.) CMOS standby current
Vcc = 5.0V
C-grade : 35mA (Max.) operating current
I- grade : 40mA (Max.) operating current
0.6uA (Typ.) CMOS standby current
High speed access time :
-70
70ns(Max.) at Vcc = 3.0V
-10
100ns(Max.) at Vcc = 3.0V
Automatic power down when chip is deselected
Three state outputs and TTL compatible
Fully static operation
Data retention supply voltage as low as 1.5V
Easy expansion with CE2, CE1, and OE options
All I/O pins are 3V/5V tolerant
FEATURES
The BS62LV2001 is a high performance, very low power CMOS
Static Random Access Memory organized as 262,144 words by 8 bits
and operates in a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.1uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
The BS62LV2001 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV2001 is available in DICE form, JEDEC standard 32 pin
450mil Plastic SOP, 8mmx13.4mm STSOP, and 8mmx20mm TSOP.
DESCRIPTION
BLOCK DIAGRAM
PRODUCT FAMILY
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
Address
Input
Buffer
Row
Decoder
Memory Array
1024 x 2048
Column I/O
Sense Amp
Write Driver
Column Decoder
Data
Buffer
Output
Address Input Buffer
A8 A3 A2 A1
A10
Data
Buffer
Input
Control
Gnd
Vdd
OE
DQ7
DQ6
DQ5
DQ4
A16
A6
A7
A15
8
DQ3
DQ2
DQ1
DQ0
A5
A4
A13
16
256
2048
1024
20
A14
A12
A9
BS62LV2001
A11
A0
OE
WE
CE1
CE2
BSI
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
A11
A9
A8
A13
WE
CE2
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
BS62LV2001TC
BS62LV2001STC
BS62LV2001TI
BS62LV2001STI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
BS62LV2001SC
BS62LV2001SI
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BS62LV2001TC | Very Low Power/Voltage CMOS SRAM 256K X 8 bit |
| BS62LV2001TI | Very Low Power/Voltage CMOS SRAM 256K X 8 bit |
| BS62LV2003 | Very Low Power/Voltage CMOS SRAM 256K X 8 bit |
| BS62LV2003SC | Very Low Power/Voltage CMOS SRAM 256K X 8 bit |
| BS62LV2003SI | Very Low Power/Voltage CMOS SRAM 256K X 8 bit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BS62LV2001TC | 制造商:BSI 制造商全稱(chēng):Brilliance Semiconductor 功能描述:Very Low Power/Voltage CMOS SRAM 256K X 8 bit |
| BS62LV2001TI | 制造商:BSI 制造商全稱(chēng):Brilliance Semiconductor 功能描述:Very Low Power/Voltage CMOS SRAM 256K X 8 bit |
| BS62LV2003 | 制造商:BSI 制造商全稱(chēng):Brilliance Semiconductor 功能描述:Very Low Power/Voltage CMOS SRAM 256K X 8 bit |
| BS62LV2003SC | 制造商:BSI 制造商全稱(chēng):Brilliance Semiconductor 功能描述:Very Low Power/Voltage CMOS SRAM 256K X 8 bit |
| BS62LV2003SI | 制造商:BSI 制造商全稱(chēng):Brilliance Semiconductor 功能描述:Very Low Power/Voltage CMOS SRAM 256K X 8 bit |
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