參數(shù)資料
型號(hào): BT16500CDL
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: 18-bit universal bus transceiver 3-State
中文描述: ABT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
封裝: 7.50 MM, PLASTIC, SOT-371-1, SSOP3-56
文件頁數(shù): 4/12頁
文件大?。?/td> 88K
代理商: BT16500CDL
Philips Semiconductors
Product specification
74ABT16500C
74ABTH16500C
18-bit universal bus transceiver (3-State)
1998 Feb 27
4
PIN DESCRIPTION
PIN NUMBER
SYMBOL
NAME AND FUNCTION
1
OEAB
A-to-B Output enable input
27
OEBA
B-to-A Output enable input (active low)
2, 28
LEAB/LEBA
A-to-B/B-to-A Latch enable input
55,30
CPAB/CPBA
A-to-B/B-to-A Clock input (active falling edge)
3, 5, 6, 8, 9, 10, 12, 13, 14, 15,
16, 17, 19, 20, 21, 23, 24, 26
A0-A17
Data inputs/outputs (A side)
54, 52, 51, 49, 48, 47, 45, 44, 43,
42, 41, 40, 38, 37, 36, 34, 33, 31
B0-B17
Data inputs/outputs (B side)
4, 11, 18, 25, 32, 39, 46, 53
GND
Ground (0V)
7, 22, 35, 50
V
CC
Positive supply voltage
FUNCTION TABLE
INPUTS
Internal
Registers
OUTPUTS
OPERATING MODE
OEAB
LEAB
CPAB
An
Bn
L
H
X
X
X
Z
Disabled
L
X
h
H
Z
Disabled Latch data
Disabled, Latch data
L
X
I
L
Z
L
L
H or L
X
NC
Z
Disabled, Hold data
L
L
h
H
Z
Disabled Clock data
Disabled, Clock data
L
L
I
L
Z
H
H
X
H
H
H
Transparent
H
H
X
L
L
L
H
X
h
H
H
Latch data & display
H
X
I
L
L
H
L
h
H
H
Clock data & display
H
L
I
L
L
H
L
H or L
X
H
H
Hold data & display
H
L
H or L
X
L
L
NOTE:
A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA, and CPBA.
H = High voltage level
h
= High voltage level one set-up time prior to the Enable or Clock transition
L
= Low voltage level
I
= Low voltage level one set-up time prior to the Enable or Clock transition
NC= No Change
X = Don’t care
Z = High Impedance “off” state
= High-to-Low Enable or Clock transition
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