參數(shù)資料
型號(hào)： BU-61582D1-131
廠商： DATA DEVICE CORP
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70
封裝： CERAMIC, DIP-70
文件頁數(shù)： 25/48頁
文件大?。?/td> 378K
代理商： BU-61582D1-131
31
Data Device Corporation
www.ddc-web.com
BU-61582
G-08/02-250
SELECT
MSB/LSB
MEM/REG
A15-A0
ADDRESS_LAT
SELECT
MSB/LSB
MEM/REG
A15-A0
(1)
(2)
(3)
(4)
(1)
(2)
(3)
(4)
(5)
t1
INTERNAL
VALUES
INPUT
SIGNALS
t2
t4
t5
t3
FIGURE 15. ADDRESS LATCH TIMING
Notes for FIGURE 15 and associated table.
1. Applicable to buffered mode only. Address SELECT AND MEM/REG latches are always transparent in the transparent mode of operation.
2. Latches are transparent when ADDR_LAT is high. Internal values do not update when ADDR_LAT is low.
3. MSB/LSB input signal is applicable to 8-bit mode only (16/8 input = logic “0”). MSB/LSB input is a “don’t care” for 16-bit operation.
ns
20
Input hold time following falling edge of ADDR_LAT
t5
ns
10
Input setup time prior to falling edge of ADDR_LAT
t4
ns
10
Propagation delay from external input signals to internal signals valid
t3
ns
10
ADDR_LAT high delay to internal signals valid
t2
ns
20
ADDR_LAT pulse width
t1
UNITS
MAX
TYP
MIN
DESCRIPTION
REF
TABLE FOR FIGURE 15. ADDRESS LATCH TIMING
相關(guān)PDF資料
PDF描述
BU-61582G1-301 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70
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