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參數(shù)資料
| 型號： | BU-61582F3-100S |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70 |
| 封裝： | CERAMIC, DFP-70 |
| 文件頁數(shù)： | 17/48頁 |
| 文件大?。?/td> | 378K |
| 代理商： | BU-61582F3-100S |
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24
Data Device Corporation
www.ddc-web.com
BU-61582
G-08/02-250
PROCESSOR INTERFACE TIMING
FIGURES 16 and 17 illustrate the timing for the host processor
to access the SP’ACE’s internal RAM or registers in the 16-bit,
nonzero wait buffered mode. FIGURE 16 illustrates the 16-bit
buffered, nonzero wait state mode read cycle timing while
FIGURE 17 shows the 16-bit, buffered, nonzero wait state mode
write cycle timing.
During a CPU transfer cycle, the signals STRB and SELECT
must be sampled low on the rising edge of the system clock to
request access to the BU-61582’s internal shared RAM. The
transfer will begin on the first rising system clock edge when
SELECT and STRBD are low and the 1553 protocol/memory
management unit is not accessing the internal RAM. The falling
edge of the output signal IOEN indicates the start of the transfer.
The SP’ACE latches the signals MEM/REG and RD/WR inter-
nally on the first falling clock edge after the start of the transfer
cycle. The address inputs latch internally on the first rising clock
edge after the signal IOEN goes low. Note that the address lines
may be latched at any time using the ADDR_LAT input signal.
The output signal READYD will be asserted low on the third (or
7th if it’s an internal read) rising system clock edge after IOEN
goes low. The assertion of READYD low indicates to the host
processor that read data is available on the parallel data bus, or
that write data has been stored. At this time, the CPU should
bring the signal STRBD high, completing the transfer cycle.
ADDRESS LATCH TIMING
FIGURE 15 illustrates the operation and timing of the address
input latches for the buffered interface mode. In the transparent
mode, the address buffers are always transparent. Since the
transparent mode requires the use of external buffers, external
address latches would be required to demultiplex a multiplexed
address bus. In the buffered mode however, the SP’ACE’s inter-
nal address latches may be used to perform the demultiplexing
function.
The ADDR_LAT input signal controls address latch operation.
When ADDR_LAT is high, the outputs of the latch (which drive
the SP’ACE’s internal memory bus) track the state of address
inputs A15 - A00. When low, the internal memory bus remains
latched at the state of A15 - A00 just prior to the falling edge of
ADDR_LAT.
MISCELLANEOUS
SELF-TEST
The BU-61582 products incorporate several self-test features.
These features include an on-line wraparound self-test for all
messages in BC and RT modes, an off-line wraparound self-test
for BC mode, and several other internal self-test features.
The BC/RT on-line loop test involves a wraparound test of the
encoder/decoder and transceiver. The BC off-line self-test
involves the encoder/decoder, but not the transceiver. These
tests entail checking the received version of every transmitted
word for validity (sync, encoding, bit count, parity) and checking
the received version of the last transmitted word for a bit-by-bit
comparison with the encoded word. The loopback test also fails
if there is a timeout of the internal transmitter watchdog timer. A
failure of the loop test results in setting a bit in the message’s
Block Status Word and, if enabled, will result in an interrupt
request. With appropriate host processor software, the BC off-
line test is able to exercise the parallel and serial data paths,
encoder, decoder, and a substantial portion of the BC protocol
and memory management logic.
There are additional built-in self-test features, involving the use
of three configuration register bits and the eight test registers.
This allows a test of approximately 99% of the J-Rad chip’s inter-
nal logic. These tests include an encoder test, a decoder test, a
register test, a protocol test, and a test of the fail-safe (transmit-
ter timeout) timer.
There is also a test mode. In the test mode, the host processor
can emulate arbitrary activity on the 1553 buses by writing to a
pair of test registers. The test mode can be operated in conjunc-
tion with the Word Monitor mode to facilitate end-to-end self-
tests.
相關(guān)PDF資料 |
PDF描述 |
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| BU-61582F3-100W | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70 |
| BU-61582F3-100Y | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70 |
| BU-61582F3-101Q | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70 |
| BU-61582F3-101S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70 |
| BU-61582F3-101Z | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70 |
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