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29
Data Device Corporation
www.ddc-web.com
BU-61582
G-08/02-250
HOST
SP'ACE
55
55
8
7
5
4
1
2
3
CH. A
TX/RXA
55
55
8
7
5
4
1
2
3
CH. B
TX/RXB
RTAD4-RTAD0
RT
ADDRESS,
PARITY
RTADP
D15-D0
+5V
-12V/-15V
CLK IN
16 MHz
CLOCK
OSCILLATOR
ADDRESS
DECODER
RESET
+5V
MSTCLR
SSFLAG/EXT_TRIG
INT
CPU INTERRUPT REQUEST
CPU D15-D0
RAM
64K x 16 MAX
WR
OE
CS
RD/WR
DTREQ
DTGRT
DTACK
A15-A0
MEMENA-IN
MEMENA-OUT
TRANSPARENT/BUFFERED
+5V
STRBD
READYD
TAG_CLK
MEMWR
MEMOE
CPU A15-A0
+5V
1553 RAM SELECT
1553 REG SELECT
MEM/REG
SELECT
CPU STROBE
CPU ACKNOWLEDGE
FIGURE 13. 16-BIT DMA MODE WITH EXTERNAL LOGIC TO REDUCE PROCESSOR ACCESS TIME TO
EXTERNAL RAM