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    參數(shù)資料
    型號(hào): BU-61582G3-430L
    廠商: DATA DEVICE CORP
    元件分類: 微控制器/微處理器
    英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70
    封裝: CERAMIC, GULL LEAD, 70 PIN
    文件頁數(shù): 18/48頁
    文件大?。?/td> 378K
    代理商: BU-61582G3-430L
    25
    Data Device Corporation
    www.ddc-web.com
    BU-61582
    G-08/02-250
    HOST
    SP'ACE
    55
    55
    8
    7
    5
    4
    1
    2
    3
    CH. A
    TX/RXA
    55
    55
    8
    7
    5
    4
    1
    2
    3
    CH. B
    TX/RXB
    RTAD4-RTAD0
    RT
    ADDRESS,
    PARITY
    RTADP
    D15-D0
    +5V
    -12V/-15V
    CLK IN
    16 MHz
    CLOCK
    OSCILLATOR
    N/C
    POLARITY_SEL
    (NOTE 2)
    ZERO_WAIT
    (NOTE 3)
    ADDRESS
    DECODER
    SELECT
    MEM/REG
    RD/WR
    STRBD
    READYD
    TAG_CLK
    RD/WR
    CPU STROBE
    CPU ACKNOWLEDGE
    (NOTE 4)
    RESET
    NOTES:
    +5V
    MSTCLR
    SSFLAG/EXT_TRIG
    INT
    CPU INTERRUPT REQUEST
    3. ZERO_WAIT SHOULD BE STRAPPED TO
    LOGIC "1" FOR NON-ZERO WAIT INTERFACE
    AND TO LOGIC "0" FOR ZERO WAIT INTERFACE.
    4. CPU ACKNOWLEDGE PROCESSOR INPUT ONLY
    FOR NON-ZERO WAIT TYPE OF INTERFACE.
    1. CPU ADDRESS LATCH SIGNAL PROVIDED BY
    PROCESSORS WITH MULTIPLEXED ADDRESS/DATA
    BUSES.
    2. IF POLARITY_SEL = "1", RD/WR IS HIGH TO READ,
    LOW TO WRITE.
    IF POLARITY_SEL = "0", RD/WR IS LOW TO READ,
    HIGH TO WRITE.
    A15-A12
    A11-A0
    N/C
    ADDR_LAT
    TRANSPARENT/BUFFERED
    CPU ADDRESS LATCH (NOTE 1)
    +5V
    16/8_BIT
    TRIGGER_SEL
    MSB/LSB
    +5V
    FIGURE 9. 16-BIT BUFFERED MODE
    相關(guān)PDF資料
    PDF描述
    BU-61582G3-430Q 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70
    BU-61582G3-430Z 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70
    BU-61582G3-431K 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70
    BU-61582G3-431W 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70
    BU-61582G3-431Y 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70
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