參數(shù)資料
      型號: BU-61582G6-120
      廠商: DATA DEVICE CORP
      元件分類: 微控制器/微處理器
      英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70
      封裝: CERAMIC, GULL LEAD, 70 PIN
      文件頁數(shù): 8/48頁
      文件大?。?/td> 378K
      代理商: BU-61582G6-120
      16
      Data Device Corporation
      www.ddc-web.com
      BU-61582
      G-08/02-250
      these words may be formulated in real time by the BU-61582
      protocol logic.
      The BU-61582 RT protocol design implements all the MIL-STD-
      1553B message formats and dual redundant mode codes. This
      design is based largely on previous generation products that
      have passed SEAFAC testing for MIL-STD-1553B compliance.
      The SP’ACE RT performs comprehensive error checking, word
      and format validation, and checks for various RT-to-RT transfer
      errors. Other key features of the BU-61582 RT include a set of
      interrupt conditions, internal command illegalization, and pro-
      grammable busy by subaddress.
      RT MEMORY ORGANIZATION
      TABLE 28 illustrates a typical memory map for the SP’ACE in RT
      mode. As in BC mode, the two Stack Pointers reside in fixed
      locations in the shared RAM address space: address 0100 (hex)
      for the Area A Stack Pointer and address 0104 for the Area B
      Stack Pointer. Besides the Stack Pointer, for RT mode there are
      several other areas of the BU-61582 address space designated
      as fixed locations. All RT modes of operation require the Area A
      and Area B Lookup Tables. Also allocated, are several fixed loca-
      tions for optional features: Command Illegalization Lookup Table,
      Mode Code Selective Interrupt Table, Mode Code Data Table,
      and Busy Bit Lookup Table. It should be noted that any unen-
      abled optional fixed locations may be used for general purpose
      storage (data blocks).
      The RT Lookup tables, which provide a mechanism for mapping
      data blocks for individual Tx/Rx/Bcst-subaddresses to areas in
      the RAM, occupy address range locations are 0140 to 01BF for
      Area A and 01C0 to 023F for Area B. The RT lookup tables
      include Subaddress Control Words and the individual Data Block
      Pointers. If used, address range 0300-03FF will be dedicated as
      the illegalizing section of RAM. The actual Stack RAM area and
      the individual data blocks may be located in any of the nonfixed
      areas in the shared RAM address space.
      RT MEMORY MANAGEMENT
      Another salient feature of the SP’ACE series products is the flex-
      ibility of its RT memory management architecture. The RT archi-
      tecture allows the memory management scheme for each trans-
      mit, receive, or broadcast subaddress to be programmable on a
      subaddress basis. Also, in compliance with MIL-STD-1553B
      Notice 2, the BU-61582 provides an option to separate data
      received from broadcast messages from nonbroadcast received
      data.
      Besides supporting a global double buffering scheme (as in BC
      mode), the SP’ACE RT provides a pair of 128-word Lookup
      Tables for memory management control, programmable on a
      subaddress basis (refer to TABLE 29). The 128-word tables
      include 32-word tables for transmit message pointers and
      receive message pointers. There is also a third, optional Lookup
      Data Block 476
      3FE0-3FFF
      Data Block 6
      0420-043F
      Data Block 5
      0400-041F
      Command Illegalizing Table (fixed area)
      0300-03FF
      RESERVED
      Data Block 1-4
      0280-02FF
      Data Block 0
      0260-027F
      (not used)
      0248-025F
      Busy Bit Lookup Table (fixed area)
      0240-0247
      Lookup Table B (fixed area)
      01C0-023F
      Lookup Table A (fixed area)
      0140-01BF
      Mode Code Data (fixed area)
      0110-013F
      Mode Code Selective Interrupt Table (fixed area)
      0108-010F
      Stack Pointer B (fixed location)
      0104
      RESERVED
      0101-0103
      Stack Pointer A (fixed location)
      0100
      Stack A
      0000-00FF
      DESCRIPTION
      ADDRESS
      (HEX)
      0105-0107
      TABLE 28. TYPICAL RT MEMORY MAP
      (SHOWN FOR 16K RAM)
      Table for broadcast message pointers, providing Notice 2 com-
      pliance, if necessary.
      RT MEMORY MANAGEMENT
      Another salient feature of the SP’ACE series products is the flexi-
      bility of its RT memory management architecture. The RT architec-
      ture allows the memory management scheme for each transmit,
      receive, or broadcast subaddress to be programmable on a sub-
      address basis. Also, in compliance with MIL-STD-1553B Notice 2,
      Subaddress
      Control Word
      Lookup Table
      (Optional)
      SACW_SA0
      .
      SACW_SA31
      0220
      .
      023F
      01A0
      .
      01BF
      Broadcast
      Lookup Table
      Optional
      Bcst_SA0
      .
      Bcst_SA31
      0200
      .
      021F
      0180
      .
      019F
      Transmit
      Lookup Table
      Tx_SA0
      .
      Tx_SA31
      01E0
      .
      01FF
      0160
      .
      017F
      Receive
      (/Broadcast)
      Lookup Table
      Rx(/Bcst)_SA0
      .
      Rx(/Bcst)_SA31
      01C0
      .
      01DF
      0140
      .
      015F
      COMMENT
      DESCRIPTION
      AREA B
      AREA A
      TABLE 29. LOOK-UP TABLES
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