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Data Device Corporation
www.ddc-web.com
BU-65170/61580/61585
H1 web-09/02-0
FIGURE 11. 16-BIT TRANSPARENT MODE USING DUAL PORT RAM
HOST
ACE
DUAL
PORT
RAM
CS-L
WR-L
OE-L
CS-R
WR-R
OE-R
MEMENA-OUT
MEMWR
MEMOE
BUSY-L
BUSY-R
N/C
CPU D15-D0
CPU ADDRESS
DIR
'245
EN
'244
EN
D15-D0
A15-A0
CPU A4-A0
A4-A0
RD/WR
ADDRESS
DECODER
1553 RAM SELECT
1553 REG SELECT
MEM/REG
IOEN
DTREQ
DTGRT
DTACK
N/C
SELECT
STRBD
CPU DATA STROBE
TRANSPARENT/BUFFERED
+5V
INT
CPU INTERRUPT REQUEST
READYD
RESET
+5V
MSTCLR
CPU READY
MEMENA-IN
+5V