參數(shù)資料
型號(hào)： BU-61703F3-160
廠商： DATA DEVICE CORP
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
封裝： CERAMIC, QFP-72
文件頁(yè)數(shù)： 16/54頁(yè)
文件大?。?/td> 576K
代理商： BU-61703F3-160
23
Data Device Corporation
www.ddc-web.com
BU-61703/61705
D1 web-09/02-0
t1
CLOCK IN rising to DTREQ low
ALL
ns
t2
DTREQ falling to DTGRT low
ALL
s
t4
DTGRT low setup prior to CLOCK IN rising edge
ALL
10
ns
t6
CLOCK IN rising to DTACK low
ALL
ns
t7
Data output valid following CLOCK IN
ALL
ns
t8
DTGRT hold time following DTACK falling
ALL
ns
t10
Data output setup time prior to MEMWR low
t12
MEMWR low pulse width
t13
CLOCK IN rising to MEMWR high
ALL
ns
t15
Data output hold time following CLOCK IN rising
ALL
10
ns
t16
CWC (all but first data word) setup time prior to MEMWR low
20 MHz
10
ns
REF
DESCRIPTION
CLOCK
FREQUENCY
VALUE @5 VOLTS
UNITS
TABLE FOR FIGURE 9. SSRT DMA WRITE (BURST MODE) TIMING
t20
GBR low pulse width
MIN
TYP
MAX
40
10
40
30
16 MHz
23
ns
12 MHz
43
ns
10 MHz
60
ns
t21
INCMD rising following CLOCK IN rising (see Note 3)
ALL
ns
30
20 MHz
10
ns
16 MHz
22
ns
12 MHz
43
ns
10 MHz
60
ns
20 MHz
90
ns
100
16 MHz
115
ns
125
12 MHz
157
ns
167
10 MHz
190
ns
200
20 MHz
40
ns
50
16 MHz
52.5
ns
62.5
12 MHz
73.3
ns
83.3
10 MHz
90
ns
100
t3
CWC setup time prior to MEMWR falling for first word of burst transfer
(see Note 1)
20 MHz
60
ns
16 MHz
85
ns
12 MHz
127
ns
10 MHz
160
ns
t5
DTGRT falling to DTACK low
20 MHz
ns
100
16 MHz
ns
113
12 MHz
ns
133
10 MHz
ns
150
t9
DTACK low pulse width (based on a two data word transfer)
(see Note 2)
20 MHz
290
ns
300
16 MHz
365
ns
375
12 MHz
490
ns
500
10 MHz
590
ns
600
t11
CLOCK IN rising to MEMWR low
ALL
ns
40
t14
Data output and CWC hold time following MEMWR high
20 MHz
20
ns
16 MHz
33
ns
12 MHz
53
ns
10 MHz
70
ns
t17
CLOCK IN rising to DTREQ and DTACK high
ALL
ns
30
t18
Data output signal Tri-State following CLOCK IN rising
ALL
ns
t19
CLOCK IN rising to GBR falling edge
ALL
ns
40
15
10
VALUE @3.3 VOLTS
MIN
TYP
MAX
40
10
40
30
40
23
43
60
40
10
22
43
60
90
100
115
125
157
167
190
200
40
50
52.5
62.5
73.3
83.3
90
100
60
85
127
160
105
118
138
155
290
300
365
375
490
500
590
600
40
10
23
43
60
40
NOTES:
(1)
Assume DTGRT is low at the time that DTREQ is asserted low. If not, then this time will increase by the amount of the DTREQ (low) - to - DTGRT (low) delay.
(2)
DTACK pulse width is 3 clock cycles per data word transfer.
(3)
Rising edge of INCMD will immediately follow the rising edge of GBR only for a broadcast message. For a non-broadcast message, the rising edge
of INCMD will occur after the mid-parity crossing of the RT status response. This additional delay time is approximately 96 clock cycles: 9.6 s at
10 MHz, 8 s at 12 MHz, 6.0 s at 16 MHz, or 4.8 s at 20 MHz.
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