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參數(shù)資料
| 型號(hào)： | BU-61703F4-142L |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 1 X 1 INCH, 0.155 INCH HEIGHT, CERAMIC, FP-72 |
| 文件頁數(shù)： | 49/52頁 |
| 文件大?。?/td> | 367K |
| 代理商： | BU-61703F4-142L |
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6
L-BRO
T/R
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
PROM / RAM / PLD
(4Kx1)
SA1
WC/MC/CWC3
WC/MC/CWC2
SA0
WC/MC/CWC4
WC/MC/CWC1
SA4
SA3
SA2
WC/MC/CWC0
I LLEG AL
A0
D0
BU - 61703 / 5
"SSRT"
(400ns max)
FIGURE 2. BU-61703/6 ILLEGALIZATION
MESSAGE PROCESSING OPERATION
Following the receipt and transfer of a valid Command Word, the
BU-61703/5 will attempt to perform one of the following opera-
tions: (1) transfer received 1553 data to the subsystem, (2) read
data from the subsystem for transmission on the 1553 bus, (3)
transmit status (and possibly the last command word or RT BIT
word) on the 1553 bus, and/or (4) set status word conditions.
The BU-61703/5 responds to all non-broadcast messages to its
RT address with a 1553 Status Word.
RT ADDRESS
RT Address 4-0 (RT_AD_4 = MSB) and RT Address Parity
(RT_AD_P) should be programmed for a unique RT address and
reflect an odd parity sum. The BU-61703/5 will not respond to any
MIL-STD-1553 commands or transfer received data from any non-
broadcast messages if an odd parity sum is not presented by
RT_AD_4-0 and RT_AD_P. An address parity error will be indicat-
ed by a low output on the
pin. The input signal
RT_AD_LAT
operates
a
transparent
latch
for
RTAD4-RTAD0 and RTADP. If RT_AD_LAT is low, the output of the
latch tracks the value presented on the input pins. If RT_AD_LAT
is high, the output of the internal latch becomes latched to the val-
ues presented at the time of a low-to-high transition of
RT_AD_LAT.
RT address and RT Address Parity must be presented valid
before the mid-parity crossing of the 1553 command and held, at
least, until following the first received data word.
RT_AD_ERR
COMMAND ILLEGALIZATION
The BU-61703/5 includes a provision for command illegalization. If
a command is illegalized, the BU-61703/5 will set the Message
error bit and transmit its status word to the Bus Controller. No data
words will be transmitted in response to an illegalized transmit
command. However, data words associated with an illegalized
receive command will be written to the external subsystem
(although these transfers may be blocked using external logic).
is sampled approximately 2 s following the mid-parity bit
zero crossing of the received command word. A low on
will illegalize a particular command word and cause the SSRT to
respond with its Message error bit set in its status word. Command
illegalization based on broadcast,
bit, subaddress, and/or
word count/mode code may be implemented by means of an
external PROM, PLD, or RAM device, as shown in FIGURE 2.
The external device may be used to define the legality of specific
commands. Any subset of the possible 1553 commands may be
illegalized as a function of broadcast,
bit, subaddress, word
count, and/or mode code. The output of the illegalization device
should be tied directly to the BU-61703/5's
signal input.
The maximum access time of the external illegalizing device is 400
ns.
If illegalization is not used,
should be hardwired to logic
"1".
ILLEGAL
R
/
T
R
/
T
ILLEGAL
相關(guān)PDF資料 |
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| BU-61703F4-142Z | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
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| BU-61703F4-152Q | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
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| BU-61703F4-162Y | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
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