參數(shù)資料
型號(hào)： BU-61703F4-162W
廠商： DATA DEVICE CORP
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
封裝： 1 X 1 INCH, 0.155 INCH HEIGHT, CERAMIC, FP-72
文件頁(yè)數(shù)： 7/52頁(yè)
文件大?。?/td> 367K
代理商： BU-61703F4-162W
15
TABLE FOR FIGURE 5. RT TRANSMIT COMMAND TIMING
VALUE
REF
DESCRIPTION
CLOCK
FREQUENCY
MIN
TYP
MAX
UNITS
t1
RT Response time.
ALL
4
6.5
7
s
t2
Mid-parity crossing of received command word delay to L-BRO,
T/R Bit, SA4-SA0, and WC/MC valid
ALL
1.5
s
t3
Mid-parity crossing of received command word delay to falling
edge of INCMD
ALL
2
s
t4
Mid-Parity crossing of receive command word delay to
MSG_ERR and HS_FAIL rising
ALL
1.5
s
t5
ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from
SA4-SA0, L-BRO, T/R, and CWC/MC valid
ALL
400
ns
t6
L-BRO, T/R, SA4-0, and WC/MC4-0 setup time prior to INCMD
low
ALL
500
ns
t7
ILLEGAL, SRV_RQST, SSFLAG, BUSY hold time following
falling edge of INCMD
ALL
300
ns
t8
Mid-Sync crossing of status word to WC/CWC valid data of 1Fh
ALL
6.5
s
20 MHz
6.75
s
16 MHz
6.81
s
12 MHz
6.92
s
t9
Mid-Sync crossing of status word to DTREQ falling edge
10 MHz
7
s
t10
Mid-Sync crossing of Status response to RT_FAIL rising (see
Note 1)
ALL
1.5
s
20 MHz
200
ns
16 MHz
250
ns
12 MHz
333
ns
t11
Duration of WC/CWC value of 1Fh
10 MHz
400
ns
t12
CWC valid following falling edge of DTREQ
ALL
30
ns
20 MHz
1.75
s
16 MHz
1.81
s
12 MHz
1.92
s
t13
Mid-Sync crossing of received data word to DTREQ falling edge
10 MHz
2
s
20 MHz
1.55
s
16 MHz
1.56
s
12 MHz
1.59
s
t14
Mid-Sync crossing of last received data word for CWC to
transition to WC
10 MHz
1.6
s
t15
Mid Parity crossing of status word to INCMD rising
ALL
3
s
NOTE1: Assuming that RTFAIL was previously low.
相關(guān)PDF資料
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