- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄223461 > BU-61703F4-172 (DATA DEVICE CORP) 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 PDF資料下載
參數(shù)資料
| 型號： | BU-61703F4-172 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 1 X 1 INCH, 0.155 INCH HEIGHT, CERAMIC, FP-72 |
| 文件頁數(shù)： | 39/52頁 |
| 文件大?。?/td> | 367K |
| 代理商： | BU-61703F4-172 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁當(dāng)前第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
44
DESCRIPTION
SIGNAL
DMA HANDSHAKE AND TRANSFER CONTROL SIGNALS
PIN
Data Transfer Acknowledge. Active low output signal used to indicate the SSRT's acceptance of the system
data bus (D15-D0), in response to a data transfer grant (DTGRT). The SSRT's data transfers over D15-D0 will
be framed by the time that DTACK is asserted low.
If AUTO_CFG is strapped to logic "0", there will be a DTREQ/DTGRT handshake cycle after the rising edge of
MSTCLR, following power turn-on. After DTGRT is sampled low, DTACK and RTACTIVE will then be asserted
low to enable configuration data to be read from an external tri-state buffer.
For transmit massages, or a receive messages in non-burst mode, or for receive messages to subaddress 30
assuming that Subaddress 30 Autowrap is disabled, DTACK will be asserted low to indicate the transfer of
individual words between the external system and the SSRT.
For receive messages in burst mode assuming a valid received message, DTACK will be asserted low after the
DTREQ-to-DTGRT handshake following the receipt of the last received data word. It will remain low for the
duration of the DMA burst write transfer from the SSRT to the external system. The total time for a burst write
transfer is three clock cycles times the number of data words.
Memory Write. Active low two-state output signal (one clock cycle wide) asserted low during SSRT write
cycles. Used to transfer data from the SSRT to the external system. The external system may latch data on
either the falling or rising edge of MEMWR.
Memory Output Enable. MEMOE two-state output signal is used to enable data inputs from the external sys-
tem to be enabled on to D15-D0. MEMOE pulses low for three clock cycles for each data word read from the
external system. The SSRT latches the data one clock cycle prior to the rising edge of MEMOE.
Handshake Fail. If this signal is asserted low, this indicates a handshake timeout condition. That is, the system
did not respond with a DTGRT in time, following the SSRT's assertion of DTREQ.
Data Transfer Grant. Input from the external subsystem that must be asserted low in response to the SSRT
asserting DTREQ low in order to enable the SSRT to read data from or write data to the external subsystem.
The maximum allowable time from DTREQ to DTGRT is 10 s.
If the SSRT's DMA handshake isn't required, DTGRT may be hardwired to logic "0".
DTACK (O)
MEMWR (O)
MEMOE (O)
HS_FAIL (O)
DTGRT (I)
29
23
14
57
64
Data Transfer Request. Active low level output signal used to request use of the external system data bus
(D15-D0).
DTREQ (O)
24
3
L_BRO (0)
Latched Broadcast. This two-state output signal is latched following receipt of a new command word. For a
broadcast command, this signal outputs a value of logic "1". For a non-broadcast message, this signal will out-
put logic "0".
4
T / R
Transmit/Receive. This two-state output signal is latched following receipt of a new command word. For a trans-
mit message, this signal will output a value of logic "1". For a receive message, this signal will output logic "0".
69
SA2 (0)
Subaddress. These five two-state output signals are latched following receipt of a new command word. They
provide the subaddress field of the received command word.
PIN
9
WC / MC / CWC2 (O)
Word Count/Mode Code/Current Word Count. Following receipt of a new command word, these five two-state
output signals provide the contents of the command word's Word Count/Mode Code field.
For a non-mode code receive message, the contents of WC/CWC are updated and incremented to reflect the
value of the current data word being transferred to the system (in non-burst mode), or to the internal FIFO (in
burst mode). CWC increments from 0 to the value of the Word Count field - 1 during the message.
At the end of a non-mode code receive message in burst mode, the contents of CWC will then increment from
0 to the value of the word count field -1, as each word is transferred from the internal FIFO to the external sys-
tem over D15-D0. In burst mode, it takes three clock cycles to transfer each word to the external system.
For a non-mode code transmit command, the value of CWC starts from 0 and increments to the value of Word
Count - 1, as each word is read from the external system and transferred to the SSRT.
For a mode code command, the WC/CWC outputs the command word mode code field, which remains latched
through the end of the message (until receipt of a subsequent command word).
COMMAND / ADDRESS BUS
SIGNAL
SA4 (0)
SA3 (0)
SA1 (0)
22
11
6
SA0 (0)
68
WC / MC / CWC4 (O) (MSB)
WC / MC / CWC3 (O)
WC / MC / CWC1 (O)
27
12
DESCRIPTION
10
WC / MC / CWC0 (O) (LSB)
15
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BU-61703F4-182S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61703F4-192S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61703G4-112Q | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72 |
| BU-61703G4-132L | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72 |
| BU-61703G4-132Y | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BU-61705 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |Simple System RT |
| BU-61740B3NEW | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |μ-ACE (Micro-ACE?) |
| BU-61743 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |Enhanced Mini-ACE? |
| BU-61743F3-100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| BU-61743F3-110 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。