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參數(shù)資料
| 型號： | BU-61703F4-192S |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 1 X 1 INCH, 0.155 INCH HEIGHT, CERAMIC, FP-72 |
| 文件頁數(shù)： | 45/52頁 |
| 文件大?。?/td> | 367K |
| 代理商： | BU-61703F4-192S |
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5
ADDRESS MAPPING:
A typical addressing scheme for the BU-61703/5 12-bit address
bus could be as follows:
A11:
A10:
A9-A5:
SUBADDRESS 4-0
A4-A0:
WORD COUNT/MODE CODE 4-0
This method of address mapping provides for a "mailbox" alloca-
tion scheme for the storage of data words. The 12 address outputs
may be used to map into 4K words of processor address space.
The BU-61703/5's addressing scheme maps messages in terms
of broadcast/own address, transmit/receive, subaddress, and
word/count mode code. A 32-word message block is allocated for
each T/R-subaddress.
For non-mode code messages, the Data Words to be transmitted
or
received
are
accessed
from
(to)
relative
locations
0 through 31 within the respective message block. For the
MIL-STD-1553B Synchronize with data, Selected transmitter shut-
down, Override selected transmitter shutdown, and Transmit vec-
tor word mode commands which involve a single data word trans-
fer, the address for the data word is offset from location 0
of the message block for subaddresses 0 and 31 by the value of
the mode code field of the received command word.
The data words transmitted in response to the Transmit last com-
mand or Transmit BIT word mode commands are accessed from
a pair of internal registers.
DMA INTERFACE
A 16-bit data bus, a 12-bit address bus, and six control signals are
provided to facilitate communication with the parallel subsystem.
The data bus D15-D0 consists of bi-directional tri-state signals.
The address bus L_BRO,
, SA4-SA0, and WC/MC/CWC4-0;
along with the data transfer control signals
and
are two-state output signals.
The control signals include the standard DMA handshake signals
,
, as well as the transfer control outputs
and
.
provides an indication to the
subsystem of a handshake failure condition.
Data transfers between the subsystem and the BU-61703/5 are
performed by means of a DMA handshake, initiated by
the BU-61703/5. A data read operation is defined to be the trans-
fer of data from the subsystem to the BU-61703/5. Conversely, a
data write operation transfers data from the BU-61703/5 to the
subsystem. Data is transferred as a single 16-bit word
FAIL
_
HS
MEMWR
MEMOE
DTACK
DTGRT
DTREQ
MEMWR
MEMOE
R
/
T
RECEIVE
/
TRANSMIT
OWNADDRESS
/
BROADCAST
DMA READ OPERATION
In response to a transmit command, the BU-61703/5 needs to
read data words from the external subsystem. To initiate a data
word read transfer, the SSRT asserts the signal
low.
Assuming that the subsystem asserts
in time, the SSRT
will then assert the appropriate values of L_BRO (logic "0"),
(high), SA4-0, and MC/CWC4-0;
high, along with
low and
low to enable data to be read from the
subsystem.
After the transfer of each Data Word has been completed, the
value of the address bus outputs CWC4 through CWC0 is incre-
mented.
DMA WRITE OPERATION
In response to a receive command, the BU-61703/5 will need to
transfer data to the subsystem. There are two options for doing
this, the burst mode and the non-burst mode. In burst mode, all
received data words are transferred from the SSRT to the subsys-
tem in a contiguous burst, only following the reception of the cor-
rect number of valid data words. In the non-burst mode,
single data words are written to the external subsystem immedi-
ately following the reception of each individual data word.
To initiate a DMA write cycle, the SSRT asserts
low. The
subsystem must then respond with
low. Assuming that
was asserted in time, the BU-61703/5 will then assert
low. The BU-61703/5 will then assert the appropriate
value of L_BRO,
, SA4-0, and MC/CWC4-0,
high,
and
low.
will be asserted low for one clock
cycle. The subsystem may then use either the falling or rising edge
of
to latch the data. Similar to the DMA read operation,
the address outputs CWC4 through CWC0 are incremented after
the completion of a DMA write operation.
HANDSHAKE FAIL
Following the assertion of
low by the SSRT, the external
subsystem has 10 s to respond by asserting
to
logic "0".
If the BU-61703/5 (SSRT) asserts
and the subsystem
does not respond with
in time for the BU-61703/5 to com-
plete a data word transfer, the
output will be asserted low
to inform the subsystem of the handshake failure, and bit 12 in the
internal Built-In-Test (BIT) word will be set to logic "1." If the hand-
shake failure occurs on a data word read transfer (for a transmit
command), the SSRT will abort the current message transmis-
sion. In the case of a handshake failure on a write transfer
(received command) the SSRT will set the handshake failure out-
put and BIT word bit, and abort processing the current message.
HSFAIL
DTGRT
DTREQ
DTACK
DTREQ
MEMWR
MEMOE
R
/
T
DTACK
DTGRT
DTREQ
MEMOE
DTACK
MEMWR
R
/
T
DTGRT
DTREQ
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| BU-61703G4-112Q | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72 |
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| BU-61703G4-132Y | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72 |
| BU-61703G4-142S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72 |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| BU-61705 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |Simple System RT |
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| BU-61743 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |Enhanced Mini-ACE? |
| BU-61743F3-100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| BU-61743F3-110 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
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