參數資料
型號: BU-61703G3-420
廠商: DATA DEVICE CORP
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
封裝: CERAMIC, QFP-72
文件頁數: 29/54頁
文件大小: 576K
代理商: BU-61703G3-420
35
Data Device Corporation
www.ddc-web.com
BU-61703/61705
D1 web-09/02-0
SIMPLE SYSTEM INTERFACE
FIGURE 17 illustrates the capability of the SSRT to interface to
a system with no host processor in burst mode. In this example,
only one set of external latches is needed to buffer the data
words written by the SSRT to the external system. In burst mode,
all received data words are stored in the internal FIFO until the
last word is received. At this point, the SSRT will transfer the
entire contents of the FIFO to the system if the message is vali-
dated. In this case, GBR will be driven low for two clock cycles
following the burst transfer cycle.
If the received message is not valid, the FIFO data will not be
transferred to the external system and GBR will remain high.
FIGURE 17. SSRT-TO-SIMPLE SYSTEM INTERFACE (Shown for BURST MODE)
D15-D0
Write
Address
Decoder
Read
Address
Decoder
LATCH
TRI-STATE
BUFFER
TRI-STATE
BUFFER
EN
TRI-STATE
BUFFER
EN
L-BRO, T/R, SA4-0,
WC/CWC4-0
MEMWR
DISCRETE
DIGITAL
INPUTS
DISCRETE
DIGITAL
OUTPUTS
AUTO-
CONFIGURATION
(OPTIONAL)
RTACTIVE
DTACK
AUTO_CFG
MEMOE
BU-61703/5
SSRT
EN
Clock
Oscillator
CLK-IN
RTAD4-0, RTADP
MSTCLR
+5V
RT
ADDRESS
BUS A
BUS B
DTGRT
+5V
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