- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄223461 > BU-61703G4-152L (DATA DEVICE CORP) 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72 PDF資料下載
參數(shù)資料
| 型號： | BU-61703G4-152L |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72 |
| 封裝： | 1 X 1 INCH, GULL WING, PACKAGE-72 |
| 文件頁數(shù)： | 14/52頁 |
| 文件大小： | 367K |
| 代理商： | BU-61703G4-152L |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
21
TABLE FOR FIGURE 8. RT-RT RECEIVE COMMAND TIMING (NON-BURST MODE)
RESPONSE TIME
REF
DESCRIPTION
CLOCK
FREQUENCY
MIN
TYP
MAX
UNITS
t1
Mid-parity crossing of received command word delay to SA4-SA0, L-
BRO, T/R Bit, and WC/MC valid
ALL
1.5
s
t2
Mid-parity crossing of received command word delay to falling edge of
INCMD
ALL
2
s
t3
Mid-Parity crossing of receive command word delay to MSG_ERR and
HS_FAIL rising
ALL
1.5
s
t4
ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from SA4-
SA0, L-BRO, T/R, and CWC/MC valid
ALL
400
ns
t5
RT Sub-Address, L-BRO, and T/R Bit setup time prior to INCMD low
ALL
500
ns
t6
ILLEGAL, SRV_RQST, SSFLAG, BUSY valid time following falling edge
of INCMD
ALL
300
ns
t7
RT – RT response timeout for transmitting RT.
ALL
17.5
18.5
19.5
s
t8
Mid-parity crossing to WC/CWC value of 1Fh
ALL
1
s
20 MHz
1.2
s
16 MHz
1.25
s
12 MHz
1.33
s
t9
Mid-parity crossing of first data word to DTREQ falling edge
10 MHz
1.4
s
20 MHz
200
ns
16 MHz
250
ns
12 MHz
333
ns
t10
WC/CWC data value of 1Fh held
10 MHz
400
ns
t11
CWC valid following falling edge of DTREQ
ALL
30
ns
t12
RT Response time.
ALL
4
6.5
7
s
t13
Delay from following mid-parity of last received data word to GBR low.
(see notes 1, 2)
ALL
4
s
t14
Mid-parity crossing of all data words, except first data word, to DTREQ
falling edge
ALL
1
s
20 MHz
100
ns
16 MHz
125
ns
12 MHz
167
ns
t15
GBR pulse width
10 MHz
200
ns
20 MHz
75
ns
16 MHz
94
ns
12 MHz
125
ns
t16
CWC transition to WC prior to Mid-Sync crossing of Status response.
10 MHz
150
ns
t17
Mid-Sync crossing of status response to RT_FAIL rising
ALL
1.5
s
t18
Mid Parity crossing of status word to INCMD rising
ALL
3.0
s
Notes:
1. Assumes that DTGRT is tied to logic "0". If DTGRT is not connected to logic "0", the minimum time to drive GBR active low
will increase by the amount of the DTGRT(low) - to - DTGRT(low) delay.
2. The transceiver delays are measured at a range of 150 ns to 450 ns for the receiver
and 100 ns to 250 ns for the transmitter.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BU-61703G4-152Y | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72 |
| BU-61703G4-152 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72 |
| BU-61703G4-162Q | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72 |
| BU-61703G4-162S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72 |
| BU-61703G4-172K | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BU-61705 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |Simple System RT |
| BU-61740B3NEW | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |μ-ACE (Micro-ACE?) |
| BU-61743 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |Enhanced Mini-ACE? |
| BU-61743F3-100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| BU-61743F3-110 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。