參數(shù)資料
型號(hào)： BU-61703G4-192Y
廠商： DATA DEVICE CORP
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72
封裝： 1 X 1 INCH, GULL WING, PACKAGE-72
文件頁(yè)數(shù)： 1/52頁(yè)
文件大?。?/td> 367K
代理商： BU-61703G4-192Y
BU-61703/61705
SIMPLE SYSTEM RT (SSRT)
COMMAND
ADDRESS
BUS
RT
MESSAGE
STATUS
RT
WORD
INPUTS
DATA
TRANSFER
CONTROL
DMA
HANDSAKE
CONTROL
DMA
HANDSAKE
AND
TRANDFER
CONTROL
LOGIC
SYSTEM
DATA
BUFFERS
DTREQ
D15-D0
DTGRT
DTACK
HS FAIL
MEMOE
MEMWR
L_BRO, T/R, SA4-SA0
WC/MC/CWC4-0
ILLEGAL
SRV_RQST
SSFLAG
BUSY
RTACTIVE
INCMD
RTAD4-RTAD0
RT_AD_LAT
RT_AD_ERR
GBR
CLK_IN
CLK_SEL1
CLK_SEL0
MSG_ERR
RTFAIL
DUAL
ENCODER
DECODER
AND
RT STATE
LOGIC
BRO_ENA
AUTO_CFG
MSTCLR
CONTROL
INPUTS
RT
ADDRESS
CLOCK
FEQUENCEY
SELECTION
55
55
55
55
TX/RX A
TX/RX B
TRANSCEIVER
A
TRANSCEIVER
B
B-3226
B-3227
B-3226
B-3227
TX_INH
BUS A
BUS B
TRANSMITTER
INHIBIT
RTADP
Note: Transformers are external.
2000 Data Device Corporation
FIGURE 1. BU-61703/5 BLOCK DIAGRAM
FEATURES
Complete Integrated Remote
Terminal Including:
Dual Low-Power 5V Only Transceiver
Complete RT Protocol Logic
Supports MIL-STD-1553A/B Notice 2,
STANAG-3838 RT, and
MIL-STD-1760 Stores Management
1.0 X 1.0 Inch, 72-pin Package
Choice of 5V or 3.3V Logic Power
Meets 1553A/McAir Response Time
Requirements
Internal FIFO for Burst Mode
Capability on Receive Data
16-bit DMA Interface
Auto Configuration Capability
Comprehensive Built-in Self-test
Direct Interface to Simple
(Processorless) Systems
Selectable Input Clock:
10, 12, 16, or 20 MHz
DESCRIPTION
The BU-61703/5 Simple System RT
(SSRT) MIL-STD-1553 terminals pro-
vide a complete interface between a
simple system and a MIL-STD-1553
bus. These terminals integrate dual
transceiver, protocol logic, and a FIFO
memory for received messages in a
1.0 inch square ceramic package. The
SSRT provides multi-protocol support
of MIL-STD-1553A/B, MIL-STD-1760,
McAir, and STANAG-3838.
The SSRT's transceivers are complete-
ly monolithic, require only a +5V sup-
ply, and consume low power. There are
versions of the simple system RT avail-
able with transceivers trimmed for MIL-
STD-1760 compliance, or compatible
to McAir standards. As a means of fur-
ther reducing power consumption, the
SSRT is available in versions with its
logic powered by +3.3V, or +5V. The
SSRT can operate with a choice of
clock frequencies of 10, 12, 16, or 20
MHz.
The SSRT is ideal for stores and other
simple systems that do not require a
microprocessor. To streamline the inter-
face to simple systems, the SSRT
includes an internal 32-word FIFO for
received data words. This serves to
ensure that only complete, consistent
blocks of validated data words are
transferred to a system.
The SSRT incorporates a built-in self-
test (BIT). This BIT, which is processed
following power turn-on or after receipt
of an Initiate self-test mode command,
provides a comprehensive test of the
SSRT's encoders, decoders, protocol,
transmitter watchdog timer, and proto-
col. The result of the built-in test may be
conveyed to the bus controller by
means of the SSRT's Terminal Flag bit
and/or its RT BIT word.
The SSRT includes an auto-configura-
tion feature. This may be used to
enable the SSRT to run (or not run) its
BIT at power turn-on, to select between
MIL-STD-1553A or -1553B protocol, to
transfer received data words to a sys-
tem either individually or by means of a
burst transfer, to implement wrap-
around for subaddress 30 (per MIL-
STD-1553B Notice 2), along with
options involving the reporting of self-
test failures and loopback errors.
相關(guān)PDF資料
PDF描述
BU-61705F4-112S 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-61705F4-162Q 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-61705G4-112 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72
BU-61705G4-152 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72
BU-61705G4-182L 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72
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