參數(shù)資料
型號: BU-61705G3-452Z
廠商: DATA DEVICE CORP
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
封裝: CERAMIC, QFP-72
文件頁數(shù): 20/54頁
文件大?。?/td> 576K
代理商: BU-61705G3-452Z
27
Data Device Corporation
www.ddc-web.com
BU-61703/61705
D1 web-09/02-0
t1
CLOCK IN rising to DTREQ low
ALL
ns
t2
DTREQ (low) - to - DTGRT delay time
ALL
s
t4
DTGRT low setup prior to CLOCK IN rising
ALL
ns
t6
CLOCK IN rising to DTACK low
ALL
ns
t7
DTGRT hold time following DTACK falling
ALL
ns
t10
MEMOE low pulse width
t11
Time for input data to become valid following falling edge of MEMOE
t12
Data input hold time following CLOCK IN rising (see Note)
ALL
30
ns
t13
CLOCK IN rising to DTREQ, DTACK, and MEMOE high
ALL
ns
REF
DESCRIPTION
CLOCK
FREQUENCY
VALUE @5 VOLTS
UNITS
TABLE FOR FIGURE 11. SSRT DMA READ TIMING
MIN
TYP
MAX
40
10
40
30
20 MHz
ns
150
16 MHz
ns
188
12 MHz
ns
250
10 MHz
ns
300
20 MHz
ns
80
16 MHz
ns
105
12 MHz
ns
146
10 MHz
ns
180
t3
CWC setup time prior to MEMOE falling
20 MHz
60
ns
16 MHz
85
ns
12 MHz
127
ns
10 MHz
160
ns
t5
DTGRT falling to DTACK low
20 MHz
ns
100
16 MHz
ns
113
12 MHz
ns
133
10 MHz
ns
150
t8
DTACK low pulse width
20 MHz
ns
200
16 MHz
ns
250
12 MHz
ns
333
10 MHz
ns
400
30
VALUE @3.3 VOLTS
MIN
TYP
MAX
40
10
40
30
40
150
188
250
300
70
95
136
170
60
85
127
160
105
118
138
155
200
250
333
400
t9
CLOCK IN rising to MEMOE low
ALL
ns
40
NOTE:
(1)
The SSRT’s data sampling time occurs one clock cycle prior to the rising edge of MEMOE.
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