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參數(shù)資料
| 型號： | BU-61705G3-502L |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | CERAMIC, QFP-72 |
| 文件頁數(shù)： | 40/54頁 |
| 文件大?。?/td> | 576K |
| 代理商： | BU-61705G3-502L |
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45
Data Device Corporation
www.ddc-web.com
BU-61703/61705
D1 web-09/02-0
DESCRIPTION
Remote Terminal Address Error. Output Signal that reflects the parity combination of the RTAD[4:0] inputs and RTADP
input. A high level indicates odd (correct) parity. A low level indicates even (incorrect) parity.
Note, if RT_AD_ERR is low, then the SSRT will not recognize any valid Command Word received to its own RT address.
RT_AD_ERR (O)
1
RT Address inputs.
RTAD0 (I) (LSB)
RTAD1 (I)
RTAD2 (I)
RTAD3 (I)
RTAD4 (I) (MSB)
33
41
21
34
35
SIGNAL
TABLE 12. RT ADDRESS
Remote Terminal Address Parity. This input signal must provide an odd parity sum with RTAD4-RTAD0 in order for the
RT to respond to non-broadcast commands. That is, there must be an odd number of logic "1"s from among RTAD-4-
RTAD0 and RTADP.
RTADP (I)
40
PIN
RT Address Latch. If RT_AD_LAT is connected to logic "0", then the SSRT is configured to accept a hardwired RT
address from RTAD4-RTAD and RTADP.
If RT_AD_LAT is initially logic "0", and then transitions to logic "1", the values presented on RTAD4-RTAD0 and RTADP
will be latched internally by the SSRT on the rising edge of RT_AD_LAT.
RT_AD_LAT (I)
31
SIGNAL
TABLE 11. DMA HANDSHAKE AND TRANSFER CONTROL SIGNALS
PIN
DTACK (O)
MEMWR (O)
MEMOE (O)
HS_FAIL (O)
DTGRT (I)
29
23
14
57
64
DESCRIPTION
Data Transfer Acknowledge. Active low output signal used to indicate the SSRT's acceptance of the system data bus
(D15-D0), in response to a data transfer grant (DTGRT). The SSRT's data transfers over D15-D0 will be framed by the
time that DTACK is asserted low.
If AUTO_CFG is strapped to logic "0", there will be a DTREQ/DTGRT handshake cycle after the rising edge of MSTCLR,
following power turn-on. After DTGRT is sampled low, DTACK and RTACTIVE will then be asserted low to enable configu-
ration data to be read from an external tri-state buffer.
For transmit messages, or receive messages in non-burst mode, or for receive messages to subaddress 30 assuming that
Subaddress 30 Autowrap is disabled, DTACK will be asserted low to indicate the transfer of individual words between the
external system and the SSRT.
For receive messages in burst mode assuming a valid received message, DTACK will be asserted low after the DTREQ-
to-DTGRT handshake following the receipt of the last received data word. It will remain low for the duration of the DMA
burst write transfer from the SSRT to the external system. The total time for a burst write transfer is three clock cycles
times the number of data words.
Memory Write. Active low two-state output signal (one clock cycle wide) asserted low during SSRT write cycles. Used to
transfer data from the SSRT to the external system. The external system may latch data on either the falling or rising
edge of MEMWR.
Memory Output Enable. MEMOE two-state output signal is used to enable data inputs from the external system to be
enabled on to D15-D0. MEMOE pulses low for three clock cycles for each data word read from the external system. The
SSRT latches the data one clock cycle prior to the rising edge of MEMOE.
Handshake Fail. If this signal is asserted low, this indicates a handshake timeout condition. That is, the system did not
respond with a DTGRT in time, following the SSRT's assertion of DTREQ.
Data Transfer Grant. Input from the external subsystem that must be asserted low in response to the SSRT asserting
DTREQ low in order to enable the SSRT to read data from or write data to the external subsystem.
The maximum allowable time from DTREQ to DTGRT is 10 s.
If the SSRT's DMA handshake isn't required, DTGRT may be hardwired to logic "0".
Data Transfer Request. Active low level output signal used to request use of the external system data bus (D15-D0).
DTREQ (O)
24
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