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參數(shù)資料
| 型號(hào)： | BU-61705G3-502Z |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | CERAMIC, QFP-72 |
| 文件頁數(shù)： | 45/54頁 |
| 文件大?。?/td> | 576K |
| 代理商： | BU-61705G3-502Z |
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5
Data Device Corporation
www.ddc-web.com
BU-61703/61705
D1 web-09/02-0
An internal Built-in-Test (BIT) Word register is updated at the end
of each message. The contents of the BIT Word Register are
transmitted in response to a Transmit BIT Word Mode Command.
The BU-61703/5 provides a number of real-time output signals.
These various signals provide indications of message in progress,
valid received message, message error, handshake fail, loop-test
fail or transmitter timeout.
The BU-61703/5 includes standard DMA handshake signals
(Request, Grant, and Acknowledge) as well as transfer control out-
puts (MEMOE and MEMWR). The DMA interface operates in a 16-
bit mode, supporting word-wide transfers.
The SSRT's system interface allows the BU-61703/5 to be inter-
faced directly to a simple system that doesn't include a micro-
processor. This provides a low-cost 1553 interface for A/D and D/A
converters, switch closures, actuators, and other discrete I/O sig-
nals.
The BU-61703/5 has an internal FIFO for received data words.
This 32-word deep FIFO may be used to allow the BU-61703/5 to
transfer its data words to the local system in burst mode. Burst
mode utilizes the FIFO by transferring data to the local bus at a
rate of one data word every three clock cycles. Burst mode nego-
tiates only once for use of the subsystem bus. Negotiation is per-
formed only after all 1553 data words have been received and val-
idated. In non-burst mode, the BU-61703/5 will negotiate for the
local bus after every received data word. The data word transfer
period is three clock cycles for each received 1553 data word.
The BU-61703/5 may also be used in a shared RAM interface con-
figuration. By means of tri-state buffers and a small amount of
"glue" logic, the BU-61703/5 will store Command Words and
access Data Words to/from dedicated "mailbox" areas in a shared
RAM for each broadcast / T/R bit / subaddress / mode code.
ADDRESS MAPPING
A typical addressing scheme for the BU-61703/5 12-bit address
bus could be as follows:
A11:
BROADCAST/OWNADDRESS
A10:
TRANSMIT/RECEIVE
A9-A5:
SUBADDRESS 4-0
A4-A0:
WORD COUNT/MODE CODE 4-0
This method of address mapping provides for a "mailbox" alloca-
tion scheme for the storage of data words. The 12 address outputs
may be used to map into 4K words of processor address space.
The BU-61703/5's addressing scheme maps messages in terms
of broadcast/ownaddress, transmit/receive, subaddress, and
word/count mode code. A 32-word message block is allocated for
each T/R-subaddress.
For non-mode code messages, the Data Words to be transmitted
or
received
are
accessed
from
(to)
relative
locations
0 through 31 within the respective message block. For the
MIL-STD-1553B Synchronize with data, Selected transmitter shut-
INTRODUCTION
GENERAL
The BU-61703/5 Simple System RT (SSRT) is a complete MIL-
STD-1553 Remote Terminal (RT) bus interface unit. Contained in
this
hybrid
are
a
dual
transceiver
and
Manchester
II
encoder/decoder, and MIL-STD-1553 Remote Terminal (RT) pro-
tocol logic. Also included are built-in self-test capability and a par-
allel subsystem interface. The subsystem interface includes a 12-
bit address bus and a 16-bit data bus that operates in a 16-bit
DMA handshake transfer configuration. The local bus and associ-
ated control signals may be operated from either +5 volt or +3.3
volt power.
The transceiver front end of the BU-61703/5 is implemented by
means of low-power monolithic technology. The transceiver
requires only a single +5 V voltage source. The voltage source
transmitters provide superior line driving capability for long cables
and heavy amounts of bus loading. In addition, the monolithic
transceivers provide a minimum stub voltage level of 20 volts
peak-to-peak transformer coupled, making the BU-61703/5 suit-
able for MIL-STD-1760 applications.
The receiver sections of the BU-61703/5 are fully compliant with
MIL-STD-1553B in terms of front-end overvoltage protection,
threshold, and bit-error rate.
The BU-61703/5 implements all MIL-STD-1553 message formats,
including all 13 MIL-STD 1553 dual redundant mode codes. Any
subset of the possible 1553 commands (broadcast, T/R bit, sub-
address, word count/mode code) may be optionally illegalized by
means of an external PROM, PLD, or RAM. An extensive amount
of message validation is performed for each message received.
Each word received is validated for correct sync type and sync
encoding, Manchester II encoding, parity, and bit count. All mes-
sages are verified to contain a legal, defined command word and
correct word count. If the BU-61703/5 is the receiving RT in an RT-
to-RT transfer, it verifies that the T/R bit of the transmit command
word is logic "1" and that the transmitting RT responds in time and
contains the correct RT address in its Status Word.
The BU-61703/5 may be operated from a 10, 12, 16, or 20 MHz
clock input. For any clock frequency, the decoder samples incom-
ing data on both edges of the clock input. This oversampling, in
effect, provides for a sampling rate of twice the input clocks' fre-
quency. Benefits of the higher sampling rate include a wider toler-
ance for zero-crossing distortion and improved bit error rate per-
formance.
The BU-61703/5 includes a hardwired RT address input. This
includes 5 address lines, an address parity input, and an address
parity error output. The RT address can also be latched by means
of a latching input signal.
The BU-61703/5 supports command illegalization. Commands
may be illegalized by asserting the input signal ILLEGAL active
low within approximately 2 s after the mid-parity bit zero-crossing
of the received command word. Command words may be illegal-
ized as a function of broadcast, T/R bit, subaddress, word count,
and/or mode code.
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