參數(shù)資料
型號(hào)： BU-61705G4-300W
廠商： DATA DEVICE CORP
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
封裝： CERAMIC, QFP-72
文件頁(yè)數(shù)： 39/54頁(yè)
文件大?。?/td> 576K
代理商： BU-61705G4-300W
44
Data Device Corporation
www.ddc-web.com
BU-61703/61705
D1 web-09/02-0
3
L_BRO (O)
Latched Broadcast. This two-state output signal is latched following receipt of a new command word. For a broadcast
command, this signal outputs a value of logic "1". For a non-broadcast message, this signal will output logic "0".
4
T / R
Transmit/Receive. This two-state output signal is latched following receipt of a new command word. For a transmit mes-
sage, this signal will output a value of logic "1". For a receive message, this signal will output logic "0".
69
SA2 (O)
Subaddress. These five two-state output signals are latched following receipt of a new command word. They provide the
subaddress field of the received command word.
PIN
9
WC / MC /
CWC2 (O)
Word Count/Mode Code/Current Word Count. Following receipt of a new command word, these five two-state output sig-
nals provide the contents of the command word's Word Count/Mode Code field.
For a non-mode code receive message, the contents of WC/CWC are updated and incremented to reflect the value of the
current data word being transferred to the system (in non-burst mode), or to the internal FIFO (in burst mode). CWC
increments from 0 to the value of the Word Count field - 1 during the message.
At the end of a non-mode code receive message in burst mode, the contents of CWC will then increment from 0 to the
value of the word count field -1, as each word is transferred from the internal FIFO to the external system over D15-D0. In
burst mode, it takes three clock cycles to transfer each word to the external system.
For a non-mode code transmit command, the value of CWC starts from 0 and increments to the value of Word Count - 1,
as each word is read from the external system and transferred to the SSRT.
For a mode code command, the WC/CWC outputs the command word mode code field, which remains latched through
the end of the message (until receipt of a subsequent command word).
TABLE 10. COMMAND / ADDRESS BUS
SIGNAL
SA4 (O)
SA3 (O)
SA1 (O)
22
11
6
SA0 (O)
68
WC / MC /
CWC4 (O) (MSB)
WC / MC /
CWC3 (O)
WC / MC /
CWC1 (O)
27
12
DESCRIPTION
10
WC / MC /
CWC0 (O) (LSB)
15
Bi-directional data bus. When the SSRT is writing data to the external system, these signals are active outputs. At all
other times, these signals are high impedance inputs.
42
D10 (I/O)
D0 (I/O) (LSB)
38
D1 (I/O)
43
D2 (I/O)
44
D3 (I/O)
D4 (I/O)
39
45
D5 (I/O)
36
D6 (I/O)
47
D7 (I/O)
46
D8 (I/O)
51
54
D9 (I/O)
52
D11 (I/O)
49
D12 (I/O)
TABLE 9. DATA BUS (16)
48
D13 (I/O)
50
D14 (I/O)
53
D15 (I/O) (MSB)
DESCRIPTION
PIN
SIGNAL NAME
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