參數(shù)資料
型號： BU-61743F4-172
廠商： DATA DEVICE CORP
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
封裝： 1 X 1 INCH, 0.155 INCH HEIGHT, FP-72
文件頁數(shù)： 42/56頁
文件大?。?/td> 321K
代理商： BU-61743F4-172
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DESCRIPTION
RTAD0 (LSB) (1)
RTAD1 (1)
RTAD2 (1)
RTAD3 (1)
RTAD4 (MSB) (1)
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SIGNAL NAME
RT ADDRESS
PIN
RT Address Latch. Input signal used to control the Enhanced MINI-ACE's internal RT address latch. If RT_AD_LAT is
connected to logic "0", then the Enhanced Mini-ACE RT is configured to accept a hardwired (transparent) RT address
from RTAD4-RTAD) and RTADP.
If RT_AD_LAT is initially logic "0", and then transitions to logic "1", the values presented on RTAD4-RTAD0 and RTADP
will be latched internally on the rising edge of RT_AD_LAT.
If RT_AD_LAT is connected to logic "1", then the Enhanced Mini-ACE's RT address is latchable under host processor
control. In this case, there are two possibilities: (1) If bit 5 of Configuration Register #6, RT ADDRESS SOURCE, is pro-
grammed to logic "0" (default), then the source of the RT Address is the RTAD4-RTAD0 and RTADP input signals; (2) If
RT ADDRESS SOURCE is programmed to logic "1", then the source of the RT Address is the lower 6 bits of the proces-
sor data bus, D5-D1 (for RTAD4-0) and D0 (for RTADP).
In either of these two cases (with RT_AD_LAT = "1"), the processor will cause the RT address to be latched by: (1) writ-
ing bit 15 of Configuration Register #3, ENHANCED MODE, to logic "1"; (2) writing bit 3 of Configuration Register #4,
LATCH RT ADDRESS WITH CONFIGURATION REGISTER #5, to logic "1"; and (3) writing to Configuration Register #5.
In the case of RT ADDRESS SOURCE = "1", then the values of RT address and RT address parity must be written to
the lower 6 bits of Configuration Register #5, via D5-D0. In the case where RT ADDRESS SOURCE = "0", the bit values
presented on D5-D0 become "don't care" .
RT_AD_LAT (1)
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Remote Terminal Address Parity. This input signal must provide an odd parity sum with RTAD4-RTAD0 in order for the
RT to respond to non-broadcast commands. That is, there must be an odd number of logic "1"s from among RTAD-4-
RTAD0 and RTADP.
RT Address inputs. If bit 5 of Configuration Register #6, RT ADDRESS SOURCE, is programmed to logic "0" (default),
then the Enhanced Mini-ACE's RT address is provided by means of these 5 input signals. In addition, if RT ADDRESS
SOURCE is logic "0", the source of RT address parity is RTADP.
There are many methods for using these input signals for designating the Enhanced Mini-ACE's RT address. For details,
refer to the description of RT_AD_LAT.
If RT ADDRESS SOURCE is programmed to logic "1", then the Enhanced Mini-ACE's source for its RT address and par-
ity is under software control, via data lines D5-D0. In this case, the RTAD4-RTAD0 and RTADP signals are not used.
RTADP (1)
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相關(guān)PDF資料
PDF描述
BU-61743G4-162S 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72
BU-61743G4-182S 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72
BU-61743G4-192L 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72
BU-61843F4-112L 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-61843G4-142Q 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
BU-61743G3-100 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC
BU-61743G3-110 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC
BU-61743G4-100 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC
BU-61743G4-110 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC
BU-61745 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |Enhanced Mini-ACE?
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