參數(shù)資料
型號(hào): BU-61845G3-300Q
廠商: DATA DEVICE CORP
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
封裝: 25.40 X 25.40 MM, 2.54 MM HEIGHT, CERAMIC, QFP-72
文件頁(yè)數(shù): 20/60頁(yè)
文件大?。?/td> 457K
代理商: BU-61845G3-300Q
27
Data Device Corporation
www.ddc-web.com
BU-6174X/6184X/6186X
F-10/02-300
RT DESCRIPTOR STACK
The descriptor stack provides a chronology of all messages
processed by the Enhanced Mini-ACE/-ACE RT. Reference
FIGURES 6, 7, and 8. Similar to BC mode, there is a four-word
block descriptor in the Stack for each message processed. The
four entries to each block descriptor are the Block Status Word,
Time Tag Word, the pointer to the start of the message's data
block, and the 16-bit received Command Word.
The RT Block Status Word includes indications of whether a par-
ticular message is ongoing or has been completed, what bus
channel it was received on, indications of illegal commands, and
flags denoting various message error conditions. For the double
buffering, subaddress circular buffering, and global circular
buffering modes, the data block pointer may be used for locating
the data blocks for specific messages. Note that for mode code
commands, there is an option to store the transmitted or
received data word as the third word of the descriptor, in place of
the data block pointer.
The Time Tag Word provides a 16-bit indication of relative time
for individual messages. The resolution of the Enhanced Mini-
ACE/-ACE's time tag is programmable from among 2, 4, 8, 16,
32, or 64 s/LSB. There is also a provision for using an external
clock input for the time tag (consult factory). If enabled, there is
a time tag rollover interrupt, which is issued when the value of
the time tag rolls over from FFFF(hex) to 0. Other time tag
options include the capabilities to clear the time tag register fol-
lowing receipt of a Synchronize (without data) mode command
and/or to set the time tag following receipt of a Synchronize (with
data) mode command. For the latter, there is an added option to
filter the "set" capability based on the LSB of the received data
word being equal to logic "0".
RT INTERRUPTS
The Enhanced Mini-ACE/-ACE offers a great deal of flexibility in
terms of RT interrupt processing. By means of the Enhanced
Mini-ACE/-ACE’s two Interrupt Mask Registers, the RT may be
programmed to issue interrupt requests for the following
events/conditions: End-of-(every)Message, Message Error,
Selected (transmit or receive) Subaddress, 100% Circular Buffer
Rollover, 50% Circular Buffer Rollover, 100% Descriptor Stack
Rollover, 50% Descriptor Stack Rollover, Selected Mode Code,
Transmitter Timeout, Illegal Command, and Interrupt Status
Queue Rollover.
Interrupts for 50% Rollovers of Stacks and Circular Buffers.
The Enhanced Mini-ACE/-ACE RT and Monitor are capable of
issuing host interrupts when a subaddress circular buffer pointer
or stack pointer crosses its mid-point boundary. For RT circular
buffers, this is applicable for both transmit and receive subad-
dresses. Reference FIGURE 9. There are four interrupt mask
and interrupt status register bits associated with the 50% rollover
function:
(1) RT circular buffer;
(2) RT command (descriptor) stack;
(3) Monitor command (descriptor) stack; and
(4) Monitor data stack.
The 50% rollover interrupt is beneficial for performing bulk data
transfers. For example, when using circular buffering for a partic-
ular receive subaddress, the 50% rollover interrupt will inform the
host processor when the circular buffer is half full. At that time,
the host may proceed to read the received data words in the
upper half of the buffer, while the Enhanced Mini-ACE/-ACE RT
writes received data words to the lower half of the circular buffer.
Later, when the RT issues a 100% circular buffer rollover inter-
rupt, the host can proceed to read the received data from the
lower half of the buffer, while the Enhanced Mini-ACE RT contin-
ues to write received data words to the upper half of the buffer.
Interrupt status queue. The Enhanced Mini-ACE/-ACE RT,
Monitor, and combined RT/Monitor modes include the capability
for generating an interrupt status queue. As illustrated in FIG-
URE 10, this provides a chronological history of interrupt gener-
ating events and conditions. In addition to the Interrupt Mask
Register, the Interrupt Status Queue provides additional filtering
capability, such that only valid messages and/or only invalid
messages may result in the creation of an entry to the Interrupt
Status Queue. Queue entries for invalid and/or valid messages
may be disabled by means of bits 8 and 7 of configuration regis-
ter #6.
The interrupt status queue is 64 words deep, providing the capa-
bility to store entries for up to 32 messages. These events and
conditions include both message-related and non-message
related events. Note that the Interrupt Vector Queue Pointer
Register will always point to the next location (modulo 64) fol-
lowing the last vector/pointer pair written by the Enhanced Mini-
ACE/-ACE RT.
The pointer to the Interrupt Status Queue is stored in the
INTERRUPT VECTOR QUEUE POINTER REGISTER (register
address 1F). This register must be initialized by the host, and is
subsequently incremented by the RT message processor. The
interrupt status queue is 64 words deep, providing the capability
to store entries for up to 32 messages.
The queue rolls over at addresses of modulo 64. The events that
result in queue entries include both message-related and non-
message-related events. Note that the Interrupt Vector Queue
Pointer Register will always point to the next location (modulo 64)
following the last vector/pointer pair written by the Enhanced
Mini-ACE/-ACE RT, Monitor, or RT/Monitor.
Each event that causes an interrupt results in a two-word entry
to be written to the queue. The first word of the entry is the inter-
rupt vector. The vector indicates which interrupt event(s)/condi-
tion(s) caused the interrupt.
The interrupt events are classified into two categories: message
interrupt events and non-message interrupt events. Message-
based interrupt events include End-of-Message, Selected mode
code, Format error, Subaddress control word interrupt, RT
Circular buffer Rollover, Handshake failure, RT Command stack
rollover,
transmitter
timeout,
MT
Data
Stack
rollover,
MT Command Stack rollover, RT Command Stack 50% rollover,
MT Data Stack 50% rollover, MT Command Stack 50% rollover,
and RT Circular buffer 50% rollover. Non-message interrupt
相關(guān)PDF資料
PDF描述
BU-61845G3-502L 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-61845G3-520K 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-61845G3-820Q 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-61845G4-320L 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-61845G4-420L 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
BU-61845G4-100 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC
BU-61845G4-110 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC
BU-61860B3NEW 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |μ-ACE (Micro-ACE?)
BU-61864 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |Enhanced Mini-ACE?
BU-61864F3-100 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC