參數(shù)資料
型號(hào)： BU-61864G4-122Y
廠商： DATA DEVICE CORP
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72
封裝： GULL WING, PACKAGE-72
文件頁(yè)數(shù)： 38/56頁(yè)
文件大?。?/td> 321K
代理商： BU-61864G4-122Y
43
PIN
SIGNAL NAME
PROCESSOR ADDRESS BUS
BU-61843(5) /
61743(5)
(4KK RAM)
DESCRIPTION
70
A12 / RTBOOT
71
A13 / Vcc -LOGIC
8
A14 / CLK_SEL_0
66
A15 / CLK_SEL_1
For BU-61864(5) (64K RAM version), this signal is always configured as address line A12. Refer
to the description for A11-A0 below.
For BU-61843(5)/61743(5) (4K RAM version), if UPADDREN is connected to logic "1", this signal
operates as A12.
For BU-61843(5)/61743(5) (4K RAM version), if UPADDREN is connected to logic "0", then this
signal functions as RTBOOT. If RTBOOT is connected to logic "0", the Enhanced Mini-ACE will
initialize in RT mode with the Busy status word bit set following power turn-on. If RTBOOT hard-
wired to logic "1", the Enhanced Mini-ACE will initialize in either Idle mode (for an RT-only part), or
in BC mode (for a BC/RT/MT part).
A12
For BU-61864(5) (64K RAM version), this signal is always configured as address line A13. Refer
to the description for A11-A0 below.
For BU-61843(5)/61743(5) (4K RAM version), if UPADDREN is connected to logic "1", this signal
operates as A13.
For BU-61843(5)/61743(5) (4K RAM version), if UPADDREN is connected to logic "0", then
this signal MUST be connected to +5V/+3.3V-LOGIC (logic "1" ).
A13
For BU-61864(5) (64K RAM version), this signal is always configured as address line A14. Refer
to the description of A11-A0 below.
For BU-61843(5)/61743(5) (4K RAM version), if UPADDREN is connected to logic "1", this signal
operates as A14.
For BU-61843(5)/61743(5) (4K RAM version), if UPADDREN is connected to logic "0", then this
signal operates as CLK_SEL_1. In this case, CLK_SEL_1 and CLK_SEL_0 are used to select the
Enhanced Mini-ACE's clock frequency, as defined in the description for A15/CLK_SEL1 above.
A14
For BU-61864(5) (64K RAM version), this signal is always configured as address line A15 (MSB).
Refer to the description for A11-A0 below.
For BU-61843(5)/61743(5) (4K RAM version), if UPADDREN is connected to logic "1", this signal
operates as address line A15.
For BU-61843(5)/61743(5) (4K RAM version), if UPADDREN is connected to logic "0", this signal
operates as CLK_SEL_1. In this case, A15/CLK_SEL_1 and A14/CLK_SEL_0 are used to select
the Enhanced Mini-ACE's clock frequency, as follows:
Clock
CLK_SEL_1
CLK_SEL_0
Frequency
0
10 MHz
0
1
20 MHz
1
0
12 MHz
1
16 MHz
A15
BU-61864(5)
(64K RAM)
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