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參數(shù)資料
| 型號(hào)： | BU-61865G3-672Y |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 25.40 X 25.40 MM, 3.94 MM HEIGHT, CERAMIC, FP-72 |
| 文件頁數(shù)： | 17/60頁 |
| 文件大?。?/td> | 700K |
| 代理商： | BU-61865G3-672Y |
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Data Device Corporation
www.ddc-web.com
BU-6174X/6184X/6186X
Rev. C
RT MEMORY MANAGEMENT
The Enhanced Mini-ACE provides a variety of RT memory man-
agement capabilities. As with the ACE and Mini-ACE, the choice
of memory management scheme is fully programmable on a
transmit/receive/broadcast subaddress basis.
In compliance with MIL-STD-1553B Notice 2, received data from
broadcast messages may be optionally separated from non-
broadcast received data. For each transmit, receive or broadcast
subaddress, either a single-message data block, a double
buffered configuration (two alternating Data Word blocks), or a
variable-sized (128 to 8192 words) subaddress circular buffer
may be allocated for data storage. The memory management
scheme for individual subaddresses is designated by means of
the subaddress control word (reference TABLE 40).
For received data, there is also a global circular buffer mode. In
this configuration, the data words received from multiple (or all)
subaddresses are stored in a common circular buffer structure.
Like the subaddress circular buffer, the size of the global circular
buffer is programmable, with a range of 128 to 8192 data words.
The double buffering feature provides a means for the host
processor to easily access the most recent, complete received
block of valid Data Words for any given subaddress. In addition
to helping ensure data sample consistency, the circular buffer
options provide a means for greatly reducing host processor
overhead for multi-message bulk data transfer applications.
End-of-message interrupts may be enabled either globally (fol-
lowing all messages), following error messages, on a
transmit/receive/broadcast subaddress or mode code basis, or
when a circular buffer reaches its midpoint (50% boundary) or
lower (100%) boundary. A pair of interrupt status registers allow
the host processor to determine the cause of all interrupts by
means of a single read operation.
Subaddress -
specific circular buffer
of specified size.
8192-Word
1
(for receive and / or broadcast subaddresses only)
Global Circular Buffer: The buffer size is specified by
Configuration Register #6, bits 11-9. The pointer to the global
circular buffer is stored at address 0101 (for Area A) or address
0105 (for Area B)
1
0
1
4096-Word
0
1
0
1
1024-Word
0
1
512-Word
1
0
256-Word
0
1
0
128-Word
1
0
For Receive or Broadcast:
Double Buffered
For Transmit: Single Message
Single Message
0
1
0
SUBADDRESS CONTROL WORD BITS
MM0
MEMORY MANAGEMENT SUBADDRESS
BUFFER SCHEME DESCRIPTION
MM1
DOUBLE-BUFFERED OR
GLOBAL CIRCULAR BUFFER
(bit 15)
MM2
TABLE 40. RT SUBADDRESS CONTROL WORD - MEMORY MANAGEMENT OPTIONS
2048-Word
1
0
1
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| BU-61865G3-710Q | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61865G3-782 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61865G3-790 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61865G4-640Z | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
相關(guān)代理商/技術(shù)參數(shù) |
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