參數(shù)資料
型號(hào)： BU-61865G4-162K
廠商： DATA DEVICE CORP
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72
封裝： GULL WING, PACKAGE-72
文件頁(yè)數(shù)： 23/56頁(yè)
文件大?。?/td> 321K
代理商： BU-61865G4-162K
3
in.
(mm)
1.0 X 1.0 X 0.155
(25.4 x 25.4 x 3.94)
°C/W
°C
s
MHz
%
20
150
+300
19.5
23.5
51.5
131
7
0.01
0.1
0.001
0.01
60
2.5
9.5
10.0
to
10.5
18.5
22.5
50.5
129.5
660.5
16.0
12.0
10.0
20.0
-55
-65
17.5
21.5
49.5
127
4
-0.01
-0.10
0.001
-0.01
40
Weight
oz
(g)
0.6
(17)
PHYSICAL CHARACTERISTICS
Size
THERMAL
Thermal Resistance, Junction-to-Case,
Hottest Die (
θJC)
Operating Junction Temperature
Storage Temperature
Lead Temperature (soldering, 10 sec.)
1553 MESSAGE TIMING
Completion of CPU Write
(BC Start)-to-Start of Next Message
for (Non-enhanced BC Mode)
BC Intermessage Gap (Note 8)
Non-enhanced
(Mini-ACE compatible) BC mode
Enhanced BC mode (Note 9)
BC/RT/MT Response Timeout (Note 10)
! 18.5 nominal
! 22.5 nominal
! 50.5 nominal
! 128.0 nominal
RT Response Time
(mid-parity to mid-sync) (Note 11)
Transmitter Watchdog Timeout
CLOCK INPUT
Frequency
! Nominal Value
Default Mode
Option
! Long Term Tolerance
1553A Compliance
1553B Compliance
! Short Term Tolerance, 1 second
1553A Compliance
1553B Compliance
! Duty Cycle
UNITS
MAX
TYP
MIN
PARAMETER
TABLE 1. EHANCED MINI-ACE SERIES SPECIFICATIONS (Cont’d)
NOTES:
Notes 1 through 6 are applicable to the Receiver Differential
Resistance and Differential Capacitance specifications:
(1)
Specifications include both transmitter and receiver (tied together
internally).
(2)
Impedance parameters are specified directly between pins TX/RX
A(B) and
of the Enhanced Mini-ACE hybrid.
(3)
It is assumed that all power and ground inputs to the hybrid are
connected.
(4)
The specifications are applicable for both unpowered and powered
conditions.
(5)
The specifications assume a 2 volt rms balanced, differential, sinu-
soidal input. The applicable frequency range is 75 kHz to 1 MHz.
(6)
Minimum resistance and maximum capacitance parameters are
guaranteed over the operating range, but are not tested.
(7)
Assumes a common mode voltage within the frequency range of
dc to 2 MHz, applied to pins of the isolation transformer on the stub
side (either direct or transformer coupled), and referenced to
hybrid ground. Transformer must be a DDC recommended trans-
former or other transformer that provides an equivalent minimum
CMRR.
(8)
Typical value for minimum intermessage gap time. Under software
control, this may be lengthened to 65,535 ms - message time, in
increments of 1 s. If ENHANCED CPU ACCESS, bit 14 of
Configuration Register #6, is set to logic "1", then host accesses
during BC Start-of-Message (SOM) and End-of-Message (EOM)
transfer sequences could have the effect of lengthening the inter-
message gap time. For each host access during an SOM or EOM
sequence, the intermessage gap time will be lengthened by 6
clock cycles. Since there are 7 internal transfers during SOM, and
5 during EOM, this could theoretically lengthen the intermessage
gap by up to 72 clock cycles; i.e., up to 7.2 ms with a 10 MHz clock,
6.0 s with a 12 MHz clock, 4.5 s with a 16 MHz clock, or 3.6 s
with a 20 MHz clock.
(9)
For Enhanced BC mode, the typical value for intermessage gap
time is approximately 10 clock cycles longer than for the non-
enhanced BC mode. That is, an addition of 1.0 s at 10 MHz, 833
ns at 12 MHz, 625 ns at 16 MHz, or 500 ns at 20 MHz.
(10) Software programmable (4 options). Includes RT-to-RT Timeout
(measured mid-parity of transmit Command Word to mid-sync of
transmitting RT Status Word).
(11) Measured from mid-parity crossing of Command Word to mid-sync
crossing of RT's Status Word.
(12) External 10 pF Tantalum and 0.1 F capacitors should be located
as close as possible to Pins 20 and 72, and a 0.1 F at pin 37. For
BU-61864 and BU-61865, there should also be a 0.1 F at pin 26.
(13) MIL-STD-1760 requires a 20 Vp-p minimum output on the stub
connection.
)
B
(
A
RX
/
TX
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