參數(shù)資料
型號(hào)： BU-62743F3-170Z
廠商： DATA DEVICE CORP
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
封裝： 1 INCH, CERAMIC, QFP-72
文件頁(yè)數(shù)： 82/99頁(yè)
文件大小： 578K
代理商： BU-62743F3-170Z
Data Device Corporation
62743_pre7_noSA-DB.DOC
www.ddc-web.com
8-07-02
83
Figure 17 illustrates a 16 Dword (32 word) PCI memory write burst, with the write
FIFO empty (or with enough free space to absorb the 16 Dwords in the FIFO).
The write FIFO accepts PCI memory writes to the ACE memory (BAR0) and ACE
registers (BAR1 offset 00h – FCh). It does not accept writes to the PCI interface
registers at BAR1 offset 800-81Ch. Writes to the BAR1 800-81Ch space go
directly into the PCI interface registers. The 32 byte write shown could be an entire
1553 message being written to ACE memory.
Writes into the BAR 0 space must be word or Dword. If only one byte
enable is asserted in a word, the PACE terminates the transaction with a Target-
Abort.
Writes into the BAR 1 00-FCh space must be word or Dword. If only one
byte enable is asserted in a word, the PACE terminates the transaction with a
Target-Abort. Since the ACE registers in this space are really 16 bit registers
packed into the lower word of a 32bit structure, only lower word or Dword writes
transfer bits into these ACE registers.
In addition, as per PCI spec, a Memory Write and Invalidate (C/BE[3:0]# =
Fh) command will be aliased to the basic Memory Write command and the timing
diagram would look the same as Figure 17.
123 456 7891011121314151617181920212223242526272829303132333435363738394041424344454647484950
51
PCI write burst to ACE memory with FIFO empty
DAT3
A DAT1 DAT2
DAT4 DAT5 DAT6 DAT7 DAT8 DAT9DAT10DAT11DAT12DAT13 DAT14
DAT15 DAT16
0ns
500ns
1000ns
1
PCICLK
AD
FRAME#
IRDY#
TRDY#
STOP#
DEVSEL#
Figure 17 PCI write burst to ACE memory w FIFO empty
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