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Data Device Corporation
62743_pre7_noSA-DB.DOC
www.ddc-web.com
8-07-02
37
RT Status Word Register and BIT Word Registers provide read-only
indications of the RT Status and BIT Words.
Test Mode Registers 0-7.
These registers are included for factory test. In
normal operation, these registers do not need to be accessed by the host
processor.
Configuration Registers #6 and #7 are used to enable the PCI Enhanced Mini-
ACE features that extend beyond the architecture of the ACE/Mini-ACE (Plus).
These includes the Enhanced BC mode; Enhanced CPU Access (note that this
bit is the only configuration bit that is SET after reset), RT Global Circular Buffer
(including buffer size); the RT/MT Interrupt Status Queue, including valid/invalid
message filtering; enabling a software-assigned RT address; clock frequency
selection; a base address for the “non-data” portion of PCI Enhanced Mini-ACE
memory; LSB filtering for the Synchronize (with data) time tag operations; and
enabling a watchdog timer for the Enhanced BC message sequence control
engine.
BC Condition Code Register is used to enable the host processor to read the
current value of the Enhanced BC Message Sequence Control Engine’s
condition flags.
BC General Purpose Flag Register allows the host processor to be able to set,
clear, or toggle any of the Enhanced BC Message Sequence Control Engine’s
General Purpose condition flags.
BIT Test Status Register is used to provide read-only access of the status of
the RAM built-in self-tests (BIT).
BC General Purpose Queue Pointer provides a means for initializing the
pointer for the General Purpose Queue, for the Enhanced BC mode. In addition,
this register enables the host to determine the current location of the General
Purpose Queue pointer, which is incremented internally by the Enhanced BC
message sequence control engine.
RT/MT Interrupt Status Queue Pointer Register provides a means for
initializing the pointer for the Interrupt Status Queue, for RT, MT, and RT/MT
modes. In addition, this register enables the host to determine the current
location of the Interrupt Status Queue pointer, which is incremented internally by
the RT/MT message processor.
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| BU-62743F3-430Z | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-62743F4-410W | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
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| BU-62743F4-500 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-62743G3-122S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
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| BU-62864 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |PCI-Enhanced Mini-ACE? |
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