參數(shù)資料
型號(hào): BU-62743F3-470
廠商: DATA DEVICE CORP
元件分類(lèi): 微控制器/微處理器
英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
封裝: 1 INCH, CERAMIC, QFP-72
文件頁(yè)數(shù): 34/99頁(yè)
文件大?。?/td> 578K
代理商: BU-62743F3-470
Data Device Corporation
62743_pre7_noSA-DB.DOC
www.ddc-web.com
8-07-02
4
Revision History
Pre7:
MISCELLANEOUS/1553 CLOCK INPUT section
Eliminate description of non-existent method of 1553 clock selection via upper
address lines
Table 18. ACE Register Address Mapping
Change internal address register 1C from “Reserved” to “BIT test status register”.
Change required ONLY for address map table.
Update ACE address maps to include PCI address offsets
Table 18. ACE Register Address Mapping, TABLE 54. TYPICAL RT MEMORY
MAP (SHOWN FOR 4K RAM), Table 55. RT Look-up Tables , Table 57.
Illegalization Table Memory Map
Rx Subaddress Double Buffering
Remove references to non-functional Rx Subaddress Double buffering feature.
Change Bit 12 of Cfg Reg #2 from “RX SA DOUBLE BUFFER ENABLE” to
“Reserved for future use, must be 0”.
Change description of Bit 15 of
Subaddress control word from “RX: DOUBLE BUFFER ENABLE ENABLE” to it’s
alternate meaning “RX: GLOBAL CIRCULAR BUFFER ENABLE”.
5V Tolerant pins
5V tolerant pins have been defined in Table 1
Figure 3. BC Op Code Format
Bit 15 in bit field was corrected from “1” to “Odd Parity”.
Table 53. Condition Codes
The description of the ALWAYS/NEVER bit was changed slightly to clarify the
description.
相關(guān)PDF資料
PDF描述
BU-62743F3-472W 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-62743F3-592S 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-62743F3-892L 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-62743F4-120Q 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-62743F4-120 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
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