參數(shù)資料
型號(hào)： BU-62743F3-592S
廠商： DATA DEVICE CORP
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
封裝： 1 INCH, CERAMIC, QFP-72
文件頁(yè)數(shù)： 3/99頁(yè)
文件大?。?/td> 578K
代理商： BU-62743F3-592S
Data Device Corporation
62743_pre7_noSA-DB.DOC
www.ddc-web.com
8-07-02
11
The PCI Enhanced Mini-ACE series terminals operate over the full military
temperature range of -55 to +125°C. Available screened to MIL-PRF-38534C,
the terminals are ideal for military and industrial processor-to-1553 applications.
TRANSCEIVERS
The transceivers in the PCI Enhanced Mini-ACE series terminals are fully
monolithic, requiring only a +5V power input.
The transmitters are voltage
sources, which provide improved line driving capability over current sources. This
serves to improve performance on long buses with many taps. The transmitters
also offer an option which satisfies the MIL-STD-1760 requirement for a
minimum of 20 volts peak-to-peak, transformer coupled output.
Besides eliminating the demand for an additional power supply, the use of a
+5V-only transceiver requires the use of a step-up, rather than a step-down,
isolation transformer.
This provides the advantage of higher terminal input
impedance than is possible for a 15 volt or 12 volt transmitter. As a result, there
is a greater margin for the input impedance test, mandated for the 1553
validation test.
This characteristic allows for longer cable lengths between a
system connector and the isolation transformers of an embedded 1553 terminal.
To provide compatibility to McAir specs, the PCI Enhanced Mini-ACE is available
with an option for transmitters with increased rise and fall times.
Additionally, for MIL-STD-1760 applications, the PCI Enhanced Mini-ACE
provides an option for a minimum stub voltage level of 20 volts peak-to-peak,
transformer coupled.
The receiver sections of the PCI Enhanced Mini-ACE are fully compliant with
MIL-STD-1553B Notice 2 in terms of front-end overvoltage protection, threshold,
common mode rejection, and word error rate.
PCI REGISTER AND MEMORY ADDRESSING
The PCI Interface contains a set of “Type 00h” PCI configuration registers that
are used to map the device into the host system. There are two Base Address
Registers that are used to implement ACE memory space (BAR0) and register
space (BAR1). The PCI configuration register space is mapped in accordance
with PCI revision 2.2 specifications.
相關(guān)PDF資料
PDF描述
BU-62743F3-892L 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-62743F4-120Q 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-62743F4-120 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-62743F4-180 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-62743F4-450Y 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
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