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參數(shù)資料
| 型號： | BU-62743F4-490Q |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 1 INCH, CERAMIC, QFP-72 |
| 文件頁數(shù)： | 88/99頁 |
| 文件大?。?/td> | 578K |
| 代理商： | BU-62743F4-490Q |
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Data Device Corporation
62743_pre7_noSA-DB.DOC
www.ddc-web.com
8-07-02
89
Table 70. SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS
MISCELLANEOUS
PIN (F & G Package)
SIGNAL NAME
BU-62864
(64K RAM)
BU-62843/62743
(4K RAM)
DESCRIPTION
INCMD* (O)/
MCRST* (O)
12
In-command or Mode Code Reset. The function of this
pin is controlled by bit 0 of Configuration Register #7,
MODE CODE RESET*/INCMD* SELECT.
If this register bit is logic “0” (default), INCMD* will be
active on this pin. For BC, RT, or Selective Message
Monitor modes, INCMD* is asserted low whenever a
message is being processed by the PCI Enhanced Mini-
ACE. In Word Monitor mode, INCMD* will be asserted
low for as long as the monitor is online.
For
RT
mode,
if
MODE
CODE
RESET/INCMD*
SELECT is programmed to logic “1”, MCRST* will be
active. In this case, MCRST* will be asserted low for two
clock cycles following receipt of a Reset remote terminal
mode command.
In
BC
or
Monitor
modes,
if
MODE
CODE
RESET/INCMD* SELECT is logic “1”, this signal is
inoperative; i.e., in this case, it will always output a value
of logic “1”.
CLOCK_IN (I)
9
20 MHz, 16 MHz, 12 MHz, or 10 MHz clock input.
TX_INH A/B(I)
15
Transmitter inhibit input for the Channel A and Channel
B MIL-STD-1553 transmitters. For normal operation, this
input should be connected to logic “0”. To force a
shutdown of Channel A and Channel B, a value of logic
“1” should be applied to the TX_INH input.
MSTCLR* (I)
2
Master Clear.
Negative true Reset input, normally
asserted low following power turn-on. When coming out
of a “reset” condition, please note that the rise time of
MSTCLR* must be less than 10 s.
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|---|---|
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| BU-62864 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |PCI-Enhanced Mini-ACE? |
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