參數(shù)資料
型號(hào)： BU-62743G3-802K
廠商： DATA DEVICE CORP
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
封裝： 1 INCH, CERAMIC, QFP-72
文件頁(yè)數(shù)： 15/99頁(yè)
文件大?。?/td> 578K
代理商： BU-62743G3-802K
Data Device Corporation
62743_pre7_noSA-DB.DOC
www.ddc-web.com
8-07-02
22
BITS 31-2 ARE RESERVED AND MUST BE WRITTEN AS 0s
CLEAR FAILSAFE INTERRUPT: Clears the Failsafe Interrupt when set to “1”.
Failsafe interrupts can also be cleared via the Failsafe Interrupt Autoclear
mechanism, enabled by bit 18 in Reg 1.
ACE RESET: Resets the ACE when set to “1”
PCI ENHANCED MINI-ACE REGISTER AND MEMORY ADDRESSING
The software interface of the enhanced Mini-ACE portion of the PCI EMA to the
host processor consists of 24 internal operational registers for normal operation,
an additional 24 test registers, plus 64K words of shared memory address space.
The PCI Enhanced Mini-ACE’s 4K X 16 or 64K X 17 internal RAM resides in this
address space.
For normal operation, the host processor only needs to access the lower 32
register address locations (00-1Fh, PCI BAR1 offset 00-7Ch). The next 32
locations (20-3F,PCI BAR1 offset 80h-FCh) should be reserved, since many of
these are used for factory test.
INTERNAL REGISTERS
The internal address mapping for the PCI Enhanced Mini-ACE registers is
illustrated in Table 18. Note that the address lines shown are the PCI Enhanced
mini-ACE’s internal ACE register bus and are left shifted 2 bits with respect to
the PCI address: A0 = PCI A2, A1 = PCI A3, etc.
For example, Interrupt mask
register #1 is located at PCI address BAR1 offset + 0h, Configuration Register
#1 is at BAR1 offset + 4h, etc. Note that the table below does not show the
internal A5 register address line, which is normally 0 and is set only for access to
the reserved factory test registers.
The configuration registers will be cleared to 0000h after hardware or
software reset, with the exception of the Enhanced CPU Access bit (bit 14 in
Configuration register #6).
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