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參數(shù)資料
| 型號： | BU-62843G3-152L |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 1 INCH, CERAMIC, QFP-72 |
| 文件頁數(shù)： | 2/99頁 |
| 文件大?。?/td> | 578K |
| 代理商： | BU-62843G3-152L |
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Data Device Corporation
62743_pre7_noSA-DB.DOC
www.ddc-web.com
8-07-02
10
INTRODUCTION
The BU-62743 RT, and BU-62843/62864 BC/RT/MT PCI Enhanced Mini-ACE
family of MIL-STD-1553 terminals comprise a complete integrated interface
between a PCI host processor and a MIL-STD-1553 bus. All members of the PCI
Enhanced Mini-ACE family are packaged in the same 1.0 square inch flatpack
package. The PCI Enhanced Mini-ACE hybrids provide footprint and software
compatibility with the Enhanced Mini-ACE, Mini-ACE (Plus) terminals, as well as
software compatibility with the older ACE series.
The PCI Enhanced Mini-ACE provides complete multiprotocol support of
MIL-STD-1553A/B/McAir and STANAG 3838. All versions integrate dual
transceiver; along with protocol, host interface, memory management logic; and
a minimum of 4K words of RAM. In addition, the BU-62864 BC/RT/MT terminals
include 64K words of internal RAM, with built-in parity checking.
The PCI Enhanced Mini-ACEs include a 5V, voltage source transceiver for
improved line driving capability, with options for MIL-STD-1760 and McAir
compatibility. To provide further flexibility, the PCI Enhanced Mini-ACE may
operate with a choice of 10, 12, 16, or 20 MHz clock inputs.
The PCI Enhanced Mini-ACEs are fully compliant targets, as defined by the PCI
Local Bus Specification Revision 2.2, using a 32 bit interface that operates at
clock speeds of up to 33 Mhz, from a 3.3V bus. The interface supports PCI
interrupts and contains a FIFO that handles PCI burst write transfer cycles. The
FIFO is deep enough to accept an entire 1553 message. The PCI interface is
NOT 5V tolerant and can not be used in a 5V PCI signaling environment. The
PCI interface is powered by 3.3V.
The 64K RAM, in the 64K version, is powered by 5V.
One of the new salient features of the PCI Enhanced Mini-ACE is its Enhanced
Bus Controller architecture. The Enhanced BC’s highly autonomous message
sequence control engine provides a means for offloading the host processor for
implementing multi-frame message scheduling, message retry schemes, data
double buffering, and asynchronous message insertion. For the purpose of
performing messaging to the host processor, the Enhanced BC mode includes a
General Purpose Queue, along with user-defined interrupts.
The PCI Enhanced Mini-ACE RT offers the choice of single and and circular
buffering for individual subaddresses. New enhancements to the RT architecture
include
a
global
circular
buffering option
for
multiple
(or
all)
receive
subaddresses, a 50% rollover interrupt for circular buffers, an interrupt status
queue for logging up to 32 interrupt events, and an option to automatically
initialize to RT mode with the Busy bit set. The interrupt status queue and 50%
rollover interrupt features are also included as improvements to the PCI
Enhanced Mini-ACE’s Monitor architecture.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BU-62843G3-180W | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-62843G3-182K | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-62843G3-200Y | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-62843G3-290S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-62843G3-412L | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BU-62864 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |PCI-Enhanced Mini-ACE? |
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| BU-62-BLU | 制造商:Mueller Electric Company 功能描述:Cable Accessories Insulator Vinyl Blue |
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| BU-62S-2 | 功能描述:INSULATOR FOR BU-60 SERIES RED 制造商:mueller electric co 系列:BU 零件狀態(tài):有效 類型:測試夾，引線，探針 配件類型:絕緣體，紅色 配套使用產(chǎn)品/相關(guān)產(chǎn)品:鱷魚夾：BU-60，BU-60C，BU-60CS，BU-60PR2，BU-60S，BU-60TBO，BU-60U，BU-60X，BU-61 規(guī)格:- 標(biāo)準(zhǔn)包裝:1 |
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