參數(shù)資料
型號: BU-62843G3-202W
廠商: DATA DEVICE CORP
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
封裝: 1 INCH, CERAMIC, QFP-72
文件頁數(shù): 90/99頁
文件大?。?/td> 578K
代理商: BU-62843G3-202W
Data Device Corporation
62743_pre7_noSA-DB.DOC
www.ddc-web.com
8-07-02
90
Table 71. SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS
PCI BUS ADDRESS AND DATA SIGNALS
SIGNAL NAME
PIN (F & G
Package)
DESCRIPTION
AD31 (I/O) (MSB)
22
AD30 (I/O)
23
AD29 (I/O)
24
AD28 (I/O)
25
AD27 (I/O)
27
AD26 (I/O)
28
AD25 (I/O)
29
AD24 (I/O)
31
AD23 (I/O)
34
AD22 (I/O)
35
AD21 (I/O)
36
AD20 (I/O)
38
AD19 (I/O)
39
AD18 (I/O)
40
AD17 (I/O)
41
AD16 (I/O)
42
AD15 (I/O)
53
AD14 (I/O)
54
AD13 (I/O)
55
AD12 (I/O)
56
AD11 (I/O)
57
AD10 (I/O)
58
AD9 (I/O)
59
AD8 (I/O)
60
AD7 (I/O)
62
AD6 (I/O)
63
AD5 (I/O)
64
AD4 (I/O)
66
AD3 (I/O)
68
AD2 (I/O)
69
AD1 (I/O)
70
AD0 (I/O) (LSB)
71
32-Bit PCI Bus Address / Data lines. Address and Data are multiplexed on the
same pins. Each bus operation consists of an address phase followed by one
or more data phases.
Address phases are identified when the control signal FRAME# is asserted.
Data transfers occur during those clock cycles in which the control signals
IRDY# and TRDY# are both asserted.
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