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參數(shù)資料
| 型號： | BU-62843G3-392 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 1 INCH, CERAMIC, QFP-72 |
| 文件頁數(shù)： | 59/99頁 |
| 文件大?。?/td> | 578K |
| 代理商： | BU-62843G3-392 |
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Data Device Corporation
62743_pre7_noSA-DB.DOC
www.ddc-web.com
8-07-02
62
RT Command stack 50% rollover, MT data stack 50% rollover, MT command
stack 50% rollover, and RT Circular buffer 50% rollover. Non-message interrupt
events/conditions include time tag rollover, RT address parity error, RAM parity
error, and BIT completed.
Bit 0 of the interrupt vector (interrupt status) word indicates whether the entry is for
a message interrupt event (if bit 0 is logic "1") or a non-message interrupt event (if
bit 0 is logic "0"). It is not possible for one entry on the queue to indicate both a
message interrupt and a non-message interrupt.
As illustrated in Figure 9, for a message interrupt event, the parameter word is a
pointer. The pointer will reference the first word of the RT or MT command stack
descriptor (i.e., the Block Status Word).
For a RAM Parity Error non-message interrupt, the parameter will be the RAM
address where the parity check failed. For the RT address Parity Error and Time
Tag Rollover non-message interrupts, the parameter is not used; it will have a
value of 0000.
If enabled, an INTERRUPT STATUS QUEUE ROLLOVER interrupt will be
issued when the value of the queue pointer address rolls over at a 64-word
address boundary.
RT COMMAND ILLEGALIZATION
The PCI Enhanced Mini-ACE provides an internal mechanism for RT Command
Word illegalizing. By means of a 256-word area in shared RAM, the host processor
may designate that any message be illegalized, based on the command word T/R
bit, subaddress, and word count/mode code fields. The PCI Enhanced Mini-ACE
illegalization scheme provides the maximum in flexibility, allowing any subset of the
4096 possible combinations of broadcast/own address, T/R* bit, subaddress, and
word count/mode code to be illegalized.
The address map of the PCI Enhanced Mini-ACE’s illegalizing table is illustrated in
Table 57.
相關(guān)PDF資料 |
PDF描述 |
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| BU-62843G3-422K | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-62843G3-432W | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-62843G3-432Z | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-62843G3-460S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-62843G3-462Y | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
相關(guān)代理商/技術(shù)參數(shù) |
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