參數(shù)資料
型號(hào)： BU-62843G3-500S
廠商： DATA DEVICE CORP
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
封裝： 1 INCH, CERAMIC, QFP-72
文件頁數(shù)： 74/99頁
文件大?。?/td> 578K
代理商： BU-62843G3-500S
Data Device Corporation
62743_pre7_noSA-DB.DOC
www.ddc-web.com
8-07-02
76
The following timing diagrams illustrate the PCI commands that the PACE
responds to.
Note that these diagrams are meant to show the basic PCI bus
operation of the PACE itself and do not show masters inserting wait states,
masters burst reading or writing past address boundaries, masters writing into a
full FIFO, etc.
To help understand the following timing diagrams an explanation of the basic
architecture of the PACE is helpful. The PACE can be thought of as the very
successful enhanced mini-ACE terminal family integrated with a 3.3V 33MHz PCI
target interface.
To simplify descriptions of the PACE architecture, the term ACE
will be used as a substitute for “enhanced mini-ACE” even though the 1553
terminal function is really an enhanced mini-ACE. When reference is made to
ACE memory (BAR0) or ACE registers (BAR1 00-FCh) these functions are part of
the ACE portion of the die. These ACE functions are accesed via the write FIFO
(for writes) and delayed read request logic (for reads).
The “PCI interface
registers” (BAR1 800-81Ch) are part of the PCI interface portion of the die and are
written and read directly from the PCI bus, without use of the write FIFO or delayed
read request logic.
The PACE’s basic PCI transaction takes 3 PCI clocks, on top of the command
phase. For example, a single write to any location within the PACE’s memory
space takes 4 PCI clocks, as shown in Figure 12. Note that this is a single write, not
an attempted burst write: FRAME# is not held asserted by the master. Also note
that a write to the ACE registers or ACE memory is actually a write into the write
FIFO whereas a write to the PCI interface registers (BAR1 800-81Ch) is a write to
the registers themselves.
1
2
3
4
5
6
7
PCI single write to any legal memory location (C/BE# = 7h)
ADRS
DATA
7h
Byte Enables
0ns
50ns
100ns
150ns
I
PCICLK
IO
AD
I
C/BE[3:0]#
I
FRAME#
I
IRDY#
O
TRDY#
O
STOP#
O
DEVSEL#
Figure 12. PCI single memory write to PACE
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