參數(shù)資料
型號: BU-62843G4-470K
廠商: DATA DEVICE CORP
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
封裝: 1 INCH, CERAMIC, QFP-72
文件頁數(shù): 86/99頁
文件大小: 578K
代理商: BU-62843G4-470K
Data Device Corporation
62743_pre7_noSA-DB.DOC
www.ddc-web.com
8-07-02
87
Table 68. SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS
PROCESSOR INTERFACE CONTROL
SIGNAL
NAME
PIN
(F & G
Package)
DESCRIPTION
SSFLAG* (I)/
EXT_TRIG (I)
14
Subsystem Flag (RT) or External Trigger (BC/Word Monitor) input.
In RT
mode, if this input is asserted low, the Subsystem Flag bit will be set in the PCI
ENHANCED MINI-ACE's RT Status Word. If the SSFLAG* input is logic "0"
while bit 8 of Configuration Register #1 has been programmed to logic "1"
(cleared), the Subsystem Flag RT Status Word bit will become logic "1," but bit
8 of Configuration Register #1, SUBSYSTEM FLAG*, will return logic "1"
when read. That is, the sense on the SSFLAG* input has no effect on the
SUBSYSTEM FLAG* register bit.
In the non-enhanced BC mode, this signal operates as an External Trigger
input.
In BC mode, if the external BC Start option is enabled (bit 7 of
Configuration Register #1), a low to high transition on this input will issue a BC
Start command, starting execution of the current BC frame.
In the enhanced BC mode, during the execution of a Wait for External Trigger
(WTG) instruction, the PCI Enhanced Mini-ACE BC will wait for a low-to-high
transition on EXT_TRIG before proceeding to the next instruction.
In the Word Monitor mode, if the external trigger is enabled (bit 7 of
Configuration Register #1), a low to high transition on this input will initiate a
monitor start. (RT the monitor on low).
This input has no effect in Message Monitor mode.
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