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| 型號(hào)： | BU-62864G4-460Z |
| 廠商： | DATA DEVICE CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 1 INCH, CERAMIC, QFP-72 |
| 文件頁(yè)數(shù)： | 10/99頁(yè) |
| 文件大?。?/td> | 578K |
| 代理商： | BU-62864G4-460Z |
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Data Device Corporation
62743_pre7_noSA-DB.DOC
www.ddc-web.com
8-07-02
18
Table 10. REG1 Fail-Safe Operation / Interrupt Register
(Read/Write 804h)
BIT
DESCRIPTION
31 (MSB)
DRR_HOLD
30
RESERVED, WRITE AS 0
22
RESERVED, WRITE AS 0
21
PCI ENHANCED MINI-ACE INTERRUPT ENABLE
20
BAR1 DRR_DATA_DISCARD INTERRUPT ENABLE
19
FAILSAFE INTERRUPT ENABLE
18
FAILSAFE INTERRUPT AUTOCLEAR ENABLE
17
FAILSAFE MODE - BIT 1 (MSB)
16
FAILSAFE MODE - BIT 0 (LSB)
15
RESERVED, WRITE AS 0
0 (LSB)
RESERVED, WRITE AS 0
This register will be all 0s after RST#, except that bit 17 will be 1 (Failsafe mode
= Failsafe Halt). Note that Failsafe errors are extremely unlikely.
DRR_HOLD: When ‘0’, a delayed read request is discarded if the PCI Enhanced
Mini-ACE has obtained requested data and a different transaction is requested.
When ‘1’, delayed read request is held until master repeats original request or
timeout occurs.
BITS 30 - 22: Reserved, write as 0s
PCI ENHANCED MINI-ACE INTERRUPT ENABLE: Must be set to “1”.
BAR1 DRR_DATA_DISCARD INTERRUPT ENABLE: Enables interrupt to occur
on a BAR1 delayed read timeout.
FAILSAFE INTERRUPT ENABLE: When set to a “1”, an interrupt is generated if
not in FAILSAFE OFF mode and a FAILSAFE error is detected.
FAILSAFE INTERRUPT AUTOCLEAR ENABLE: If set, causes interrupt and the
FAIL_SAFE ERROR bit (REG0-bit 22) to be cleared whenever upper word of
REG0 is read by the PCI MASTER. If not set, bit 1 in Reg 7 must be used to
clear Failsafe interrupts.
FAILSAFE MODE: Fail Safe Errors occur when the internal ACE fails to assert
it’s hand-shake signal within 1 millisecond (programmable) of when the internal
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