參數資料
型號: BU-62864G4-470S
廠商: DATA DEVICE CORP
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
封裝: 1 INCH, CERAMIC, QFP-72
文件頁數: 33/99頁
文件大?。?/td> 578K
代理商: BU-62864G4-470S
Data Device Corporation
62743_pre7_noSA-DB.DOC
www.ddc-web.com
8-07-02
39
The operation of the PCI Enhanced Mini-ACE’s message sequence control engine
is illustrated in Figure 2. The BC message sequence control involves an instruction
list pointer register; an instruction list which contains multiple 2-word entries; a
message control/status stack, which contains multiple 8-word or 10-word
descriptors; and data blocks for individual messages.
The
initial value of the instruction list pointer register is initialized by the host
processor (via Register 0D), and is incremented by the BC message sequence
processor (host readable via Register 03). During operation, the message
sequence control processor fetches the operation referenced by the instruction list
pointer register from the instruction list.
OP CODE
DATA BLOCK
MESSAGE
CONTROL/STATUS
PARAMETER
(POINTER)
BLOCK
BC INSTRUCTION
LIST
BC INSTRUCTION
LIST POINTER REGISTER
BC CONTROL
WORD
COMMAND WORD
(Rx Command for
RT-to-RT transfer)
DATA BLOCK POINTER
TIME-TO-NEXT MESSAGE
TIME TAG WORD
BLOCK STATUS WORD
LOOPBACK WORD
RT STATUS WORD
2nd COMMAND WORD
(for RT-to-RT transfer)
2nd RT STATUS WORD
(for RT-to-RT transfer)
INITIALITIZE BY REGISTER
0D (RD/WR); READ CURRENT
VALUE VIA REGISTER 03
(RD ONLY)
Figure 2. BC Message Sequence Control
相關PDF資料
PDF描述
BU-62864G4-800Y 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-62864G4-890L 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-62743F3-170Z 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-62743F3-182L 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-62743F3-400W 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
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