參數(shù)資料
型號: BU-63825D1-301
廠商: DATA DEVICE CORP
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70
封裝: CERAMIC, DIP-70
文件頁數(shù): 18/48頁
文件大小: 405K
代理商: BU-63825D1-301
25
Data Device Corporation
www.ddc-web.com
BU-63825
C-02/06-0
HOST
SP'ACE II
55
55
8
7
5
4
1
2
3
CH. A
TX/RXA
55
55
8
7
5
4
1
2
3
CH. B
TX/RXB
RTAD4-RTAD0
RT
ADDRESS,
PARITY
RTADP
D15-D0
+5V
-12V/-15V
CLK IN
16 MHz
CLOCK
OSCILLATOR
ZERO_WAIT
(NOTE 2)
ADDRESS
DECODER
SELECT
MEM/REG
RD/WR
STRBD
READYD
TAG_CLK
RD/WR
CPU STROBE
CPU ACKNOWLEDGE
(NOTE 4)
RESET
NOTES:
+5V
MSTCLR
SSFLAG/EXT_TRIG
INT
CPU INTERRUPT REQUEST
3. ZERO WAIT SHOULD BE STRAPPED TO LOGIC "1" FOR
NON-ZERO WAIT INTERFACE AND TO LOGIC "0" FOR
ZERO WAIT INTERFACE.
4. CPU ACKNOWLEDGE PROCESSOR INPUT ONLY FOR NON-ZERO
WAIT TYPE OF INTERFACE.
1. CPU ADDRESS LATCH SIGNAL PROVIDED BY PROCESSORS
WITH MULTIPLEXED ADDRESS/DATA BUSES.
2. IF POLARITY_SEL = "1", THEN RD/WR IS HIGH TO READ.
LOW TO WRITE.
IF POLARITY_SEL = "0", THEN RD/WR IS LOW TO READ.
HIGH TO WRITE.
A15-A14
A13-A0
N/C
ADDR_LAT
CPU ADDRESS LATCH
TRANSPARENT/BUFFERED
+5V
(NOTE 1)
POLARITY_SEL
(NOTE 3)
+5V
16/8_BIT
N/C
TRIGGER_SEL
MSB/LSB
FIGURE 9. 16-BIT BUFFERED MODE
相關PDF資料
PDF描述
BU-63925F0-200 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70
BU-63925G6-190 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70
BU-63825D3-200 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70
BU-63825G1-300 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70
BU-63925D6-191 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70
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