參數(shù)資料
型號： BU-64703B4-300
廠商： DATA DEVICE CORP
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CBGA80
封裝： CERAMIC, BGA-80
文件頁數(shù)： 23/48頁
文件大?。?/td> 405K
代理商： BU-64703B4-300
3
Data Device Corporation
www.ddc-web.com
BU-64703
D-03/06-0
V
A
V
mA
pF
0.7
0.2Vcc
10
-33
10
0.4
-2.2
50
2.1
0.8Vcc
0.4
1.0
-10
-350
-10
2.4
2.2
LOGIC
VIH
All signals except CLOCK_IN
CLOCK_IN
VIL
All signals except CLOCK_IN
CLOCK_IN
Schmidt Hysteresis
All signals except CLOCK_IN
CLOCK_IN
IIH, IIL
All signals except CLOCK_IN
IIH (Vcc=3.6V, VIN=Vcc)
IIH (Vcc=3.6V, VIH=2.7V)
IIL (Vcc=3.6V, VIH=0.4V)
CLOCK_IN
IIH
IIL
VOH (Vcc=3.0V, VIH=2.7V,
VIL=0.2V, IOH=max)
VOL (Vcc=3.0V, VIH=2.7V,
VIL=0.2V, IOL=max)
IOL (Vcc = 3.0V)
IOH (Vcc = 3.0V)
CI (Input Capacitance)
CIO (Bi-directional signal input
capacitance)
Vp-p
mVp-p
mVpeak
nsec
9
27
10
250
300
7
20
21.5
150
250
6
18
20
-250
100
200
TRANSMITTER
Differential Output Voltage (Note 8)
Direct Coupled Across 35
,
Measured on Bus
Transformer Coupled Across
70
, Measured on Bus
BU-64703XX-XX0
BU-64703X8/3-XX2 (Note 9)
Output Noise, Differential (Direct
Coupled)
Output Offset Voltage, Transformer
Coupled Across 70 ohms
Rise/Fall Time
BU-64703X8/3
BU-64703X9/4
k
pF
Vp-p
Vpeak
5
0.860
10
2.5
0.200
RECEIVER
Differential Input Resistance
(Notes 1-6)
Differential Input Capacitance
(Notes 1-6)
Threshold Voltage, Transformer
Coupled, Measured on Stub
Common Mode Voltage (Note 7)
V
6.0
4.5
7.0
6.0
-0.3
ABSOLUTE MAXIMUM RATING
Supply Voltage
Logic +3.3V
Transceivers +3.3V (Note 10)
(not during transmit)
Transceiver +3.3V
(during transmit) (Note 10)
Transceiver +5.0V
+3.3V Logic Input Range
UNITS
MAX
TYP
MIN
PARAMETER
TABLE 1. SSRT Mark3 SPECIFICATIONS
W
V
mA
UNITS
MAX
TYP
MIN
PARAMETER
0.31
0.69
1.04
1.74
0.31
0.71
1.08
1.83
0.63
0.85
1.07
1.51
0.63
0.86
1.09
1.56
0.09
0.47
0.82
1.52
0.09
0.49
0.85
1.61
3.60
3.46
5.25
95
300
500
900
95
315
535
975
100
205
310
520
40
100
216
332
565
40
3.3
5.0
3.00
3.14
4.75
POWER DISSIPATION
Total Hybrid (Notes 8, 11 and 14)
BU-64703X8/9-XX0, (1553 & McAir)
Idle
25% Transmitter Duty Cycle
50% Transmitter Duty Cycle
100% Transmitter Duty Cycle
BU-64703X8-XX2, (1760)
Idle
25% Transmitter Duty Cycle
50% Transmitter Duty Cycle
100% Transmitter Duty Cycle
BU-64703X3/4-X00, (1553 & McAir)
Idle
25% Transmitter Duty Cycle
50% Transmitter Duty Cycle
100% Transmitter Duty Cycle
BU-64703X3-X02, (1760)
Idle
25% Transmitter Duty Cycle
50% Transmitter Duty Cycle
100% Transmitter Duty Cycle
Hottest Die
BU-64703X8/9-XX0 (1553 &McAir)
Idle
25% Transmitter Duty Cycle
50% Transmitter Duty Cycle
100% Transmitter Duty Cycle
BU-64703X8-XX2 (1760)
Idle
25% Transmitter Duty Cycle
50% Transmitter Duty Cycle
100% Transmitter Duty Cycle
POWER SUPPLY REQUIREMENTS
Voltages/Tolerances
+3.3V Logic
+3.3V Transceivers (Note 10)
+5.0V Transceivers
Current Drain(Total Hybrid)(Notes 8,14)
BU-64703X8/9-XX0,(1553 & McAir)
Idle
25% Transmitter Duty Cycle
50% Transmitter Duty Cycle
100% Transmitter Duty Cycle
BU-64703X8-XX2, (1760)
Idle
25% Transmitter Duty Cycle
50% Transmitter Duty Cycle
100% Transmitter Duty Cycle
Current Drain(Total Hybrid)(Notes 8,14)
BU-64703X3/4-X00,(1553 & McAir)
+5V (Ch. A, Ch. B)
Idle
25% Transmitter Duty Cycle
50% Transmitter Duty Cycle
100% Transmitter Duty Cycle
3.3V Logic
BU-64703X3-X02,(1760)
+5V (Ch. A, Ch. B)
Idle
25% Transmitter Duty Cycle
50% Transmitter Duty Cycle
100% Transmitter Duty Cycle
3.3V Logic
TABLE 1. SSRT Mark3 SPECIFICATIONS (Cont’d)
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