參數(shù)資料
型號(hào)： BU-65142D1-490K
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁(yè)數(shù)： 13/24頁(yè)
文件大?。?/td> 219K
代理商： BU-65142D1-490K
20
These pins are not used on this package.
Status Word Enable-- LOW level active
output signal present when the status
word is enabled on the parallel data bus.
N/C
STATEN
1,41,
42,82
44
Low output to the primary side of the
coupling transformer that connects to the
A channel of the 1553 Bus.
TXDATA A
46
Not connected.
N/C
48
Power supply return connection for the A
channel transceiver.
GND A
50
Input from the HIGH side of the primary
side of the coupling transformer that con-
nects to the A channel of the 1553 Bus.
RXDATA A
52
Message Error--output signal that goes
LOW and stays LOW whenever there is a
format or word error with the received
message over the 1553 Data Bus.
Cleared by the next NGBT.
ME
54
_
41
_
78
43
77
45
76
47
75
49
74
73
51
FUNCTION
78-
Pin
Flat-
Pack
DESCRIPTION
PACKAGE & PIN
82-
Pin
Flat-
Pack
PIN FUNCTION TABLE (continued)
1.800 MAX
(46)
1.500
(38)
1.800 (46)
INDEX
DENOTES
PIN 1
2.100 MAX
(53)
1.900 (48)
0.210
MAX
(5.33)
0.100 TYP (2.54)
0.250 ±0.010
(6.35 ±0.25)
PIN NUMBERS FOR
REFERENCE ONLY
1.650
(42)
0.018 ±0.002 DIA TYP
(0.46 ±0.05)
59
20
40
78
60
21
41
1
2
SEE DETAIL "A"
0.050 TYP (1.27)
DETAIL "A"
NOTE: DIMENSIONS ARE IN INCHES (MM).
PIN FUNCTION TABLE NOTES:
1. TEST 2
This pin provides the output of the BUS-65142 BIT Comparison out-
put. It indicates the loop test results for every word transmitted by
the BUS-65142. A test can be performed by actioning the RTU to
transmit while the test fixture opens the receiver lines to force an
error condition. A logic 1 (high) indicates the loop test passed.
Normally this pin is left open.
2.
This pin is typically tied to
, causing the BUS-65142 to drive
the shared data bus only while
is active. If desired
can be grounded. The data will remain latched on the data bus pins
for 18s from
and 3.5s for the last word of a message as
the device’s status word or BIT word is transferred to the BC
(
or
low). Once the STATUS or BIT Word transfer is
complete, the data bus will automatically again contain the last data
word. The BUS-65142 will automatically switch the direction of the
internal buffers during a transmit operation.
3.
This test allows the user to force the active channel to transmit inde-
finetly, in order to test the built in Watchdog Timer feature of the
BUS-65142. When this pin is grounded and the active channel is
stimulated with a valid transmit command, the BUS-65142 will
respond with a status word and contiguous data (last data word
loaded or STATUS WORD if none is loaded) until the built-in time out
occurs. Normally this pin is left open or an optional pull-up can be
used.
4. PINS 1, 41, 42, 82 for BUS-65144/45 82-pin Flat Pack, FIGURE 8
are not connected (N/C).
5. -VA and -VB are not connected (N/C) for BU-65142X3.
1
TEST
BITEN
STATEN
DTSRB
ENA
BUF
DTACK
ENA
BUF
FIGURE 7. BUS-65142/43 MECHANICAL OUTLINE (STANDARD PRODUCT)
(78-PIN KOVAR QIP)
78-
Pin
QIP
相關(guān)PDF資料
PDF描述
BU-65142D1-490L Controller Miscellaneous - Datasheet Reference
BU-65142D1-490Q Controller Miscellaneous - Datasheet Reference
BU-65142D1-490S Controller Miscellaneous - Datasheet Reference
BU-65142D1-490W Controller Miscellaneous - Datasheet Reference
BU-65142D1-490Y Controller Miscellaneous - Datasheet Reference
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