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| 型號： | BU-65142F2-210 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP78 |
| 封裝： | CERAMIC, DFP-78 |
| 文件頁數(shù)： | 21/26頁 |
| 文件大?。?/td> | 247K |
| 代理商： | BU-65142F2-210 |
4
Data Device Corporation
www.ddc-web.com
BU-65142 and BUS-65142 SERIES
U-05/02-0
INTRODUCTION
The BUS-65142 is a complete dual redundant Remote Terminal
Unit (RTU). It is fully compliant with MIL-STD-1553B and sup-
ports all message formats. As shown in FIGURE 1, it includes
2 transceivers and a custom chip containing 2 encoders, 2 bit
processors, an RTU protocol sequencer and control logic, output
latches, and buffers. With the addition of 2 data bus transform-
ers, the BUS-65142 is ready for connection to a MIL-STD-1553
data bus.
Data is transferred to and from the subsystem host CPU over a
16-bit parallel highway, which is isolated by a set of bi-direction-
al buffers. All transfers are made with a DMA type handshake
sequence of request, grant and acknowledge. Read/write and
data strobes are provided to simplify interfacing to external
RAM. Also simplifying the RAM interface is the availability of a
latched command word and an auto-incrementing word counter.
These signals may be used as an address to map the data
directly to and from RAM.
The BUS-65142 allows the subsystem host CPU to control 6 of
the bits in the RTU status word. Of particular interest is the
Illegal Command input which may be used to set the message
error bit and illegalize any command word. The BUS-65142 pro-
vides four error flags to the subsystem host CPU for evaluating
its condition. In addition a continuous on-line self-test is per-
formed by the BUS-65142 on every transmission. The last
Transmitted Word of every message is wrapped around the
decoder and compared with the Actual Word. Any discrepancy
is flagged as an error.
TIMING
Interfacing the subsystem host CPU to the BUS-65142 is simple
and compatible with most microprocessors. FIGURES 4 and 5
illustrate typical MIL-STD-1553 messages for Transmit data and
Receive data. FIGURES 6 and 7 illustrate RT to RT transfers. In
each case NBGT identifies the start of the message, and
INCMD identifies that a command is being processed. The hand-
shake sequence DTREQ , DTGRT, and DTACK is used to trans-
fer each word over the parallel data highway.
DTSRB and
RD/WR are used to control transfers to RAM memory. GBR
identifies a “good block received”, when a received message has
passed all validation checks and has the correct word count.
BUFENA (Buffer Enable) must be applied to enable the internal
tri-state buffers.
ERROR FLAGS
Four error flags are output to the subsystem to provide informa-
tion on the condition of the BUS-65142.
The ME (Message Error) line goes LOW if any of the fol-
lowing error conditions exist:
format error
word count error
invalid word
sync error
RT to RT address error
T/R bit error.
The RTFAIL (Remote Terminal Failure) line goes LOW
whenever the results of a continuous wraparound self-test
shows a discrepancy, or a transmitter watchdog timeout
has occurred.
The HSFAIL (Handshake Failure) line goes LOW whenev-
er the system does not issue a DTGRT in response to a
DTREQ before timing-out.
The RTADR ERR (RT Address Error) line goes LOW when-
ever the sum of the 5 address lines and parity lines show a
parity error (the terminal will not respond to commands
while this error condition exists).
STATUS REGISTER
Six inputs to the BUS-65142 allow the subsystem host CPU to
control bits in the RTU status word. The Illegal Command input
may be used to set the Message Error bit in the Status Word and
suppress the transmission of data to the bus controller. This line
allows illegalization of any combination of commands. The
latched Command Word may be connected to the address pins
of an optional external PROM, which would drive the illegal
Command line LOW when it identifies a command programmed
as illegal.
STATUS REGISTER BIT ASSIGNMENTS
The SRQ (Subsystem Request) line is used to set the
Status Word service request bit.
The ADBC (Accept Dynamic Bus Control) line is used to
set the Status Word bus control bit.
The RTFLAG (RT Flag Line) is used to set the Status Word
terminal flag bit.
The BUSY (Busy) line is used to set the Status Word busy
bit, and inhibit subsystem requests for data.
The SSFLAG (SubSystem Flag) line is used to set the
Status Word subsystem (fault) flag.
BUILT-IN-TEST
The BUS-65142 contains a 14-bit Built-In-Test (BIT) word regis-
ter which stores information about the condition of the RTU.
When a mode code is received to transmit the BIT word, the con-
tents of the BIT register is transmitted over the 1553 bus.
FIGURE 2 shows the fault assigned to each bit in the BIT word.
Conditions monitored are; transmitter timeouts, loop test failures,
transmitter shutdown, subsystem handshake failure, and the
results of individual message validations.
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