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參數(shù)資料
| 型號： | BU-65566M49N |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), MIL-STD-1553 CONTROLLER, XMA64 |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 502K |
| 代理商： | BU-65566M49N |
5
Data Device Corporation
www.ddc-web.com
BU-65566
F-04/06-0
For the BU-65566GX-200 card, the rail temperature can range
from -40°C to +85°C. DDC has designed this board to operate
under these temperature conditions.
MECHANICAL DESIGN
Test specimens of the BU-65566 card were subjected to Shock
and Random Vibration testing. All devices were non-operational
during all phases of testing and exhibited no evidence of physi-
cal damage at the conclusion of testing.
Three (3) shock pulses were applied in each of the following six
(6) test directions: Horizontal (+X), Horizontal (+Z), Vertical (+Y),
Horizontal (-X), Horizontal (-Z), and Vertical (-Y). Each applied
shock pulse was Half-Sine in wave shape, at an input amplitude
of 40 g's and a duration of 11 milliseconds.
Random vibration was independently applied for one (1) hour to
each of three (3) orthogonal axes resulting in a total test time of
three (3) hours. Testing was performed with the input applied
along the Horizontal (X), Horizontal (Z) and Vertical (Y) test axes.
Test specimens were subjected to a Random input, in the fre-
quency range of 15 to 2000 Hz at .1g2 / Hz.
PMC cards are optionally conformally coated with Humiseal
1A33 polyurethane coating. Please see the ordering information
in the back of this data sheet for details.
PCI INTERFACE
As a means of minimizing power consumption and dissipation,
the design of the standard BU-65566 card utilizes +3.3 volt
power for the PCI interface and 1553 (Enhanced Mini-ACE)
logic. The 1553 transceivers and RAM are powered by +5 volts.
The default configuration of the BU-65566GX card provides an
on board voltage regulator for applications where +3.3 volt power
is not available. On the other hand, the BU-65566MX requires
that both +5.0V and +3.3V be available on the PMC connector.
DDC is able to supply a non-standard version of the BU-65566GX card
where the voltage regulator is removed and the card will utilize the +3.3V
power supply pins on the PMC connector (consult factory).
The BU-65566's PCI interface is a fully compliant target (slave)
agent, as defined by the PCI Local Bus Specification Revision
2.2, using a 32-bit interface that operates at clock speeds of up
to 66 MHz, in a +3.3 volt or +5 volt signaling environment. The
interface supports PCI interrupts and contains a 72 X 32 FIFO to
accelerate burst write transfers from the PCI host.
INTERRUPTS
The Enhanced Mini-ACE's may issue interrupt requests over the
PCI bus. PCI interrupts are generated on the INTA# output sig-
nal to the PCI host. The interrupts from each Enhanced Mini-
ACE(s) are logically Or'ed together to provide a single interrupt
for the card.
REGISTER AND MEMORY ADDRESSING
The BU-65566 PCI interface contains a set of "Type 00h" PCI
configuration registers that are used to map the device into the
host system. The PCI configuration register space is mapped in
accordance with PCI revision 2.2 specifications. These registers
are arranged such that all Enhanced Mini-ACE memory and reg-
ister space may be addressed through a single PCI function.
The PCI configuration space of this card is described in the BU-
65565/66 Card Manual. When using this card with one of DDC's
drivers and the Enhanced Mini-ACE API library software, the
details of these registers and memory addresses are abstracted
from the user.
ENHANCED MINI-ACE REGISTER AND
MEMORY ADDRESSING
The software interface between each Enhanced Mini-ACE and
the PCI host consists of 24 internal operational registers for nor-
mal operation, an additional space for 40 test mode registers,
and 64K words of shared memory address space.
Enhanced Mini-ACE registers may only be accessed as 16-bit
words. If a 32-bit read access is attempted, the upper 16 bits will
not be valid. That is, register accesses are on a 32-bit boundary
(e.g., 000 = Enhanced Mini-ACE Register 0, 004 = Enhanced
Mini-ACE Register 1, 008 = Enhanced Mini-ACE Register 2,
etc). For normal operation, the host processor only needs to
access the lower 32 register address locations (00-1F). The next
32 locations (20-3F) should be reserved, since many of these
are used for factory test.
Enhanced Mini-ACE memory may be accessed as either single
16-bit words, or as a 32-bit double word. For the latter, a packed
pair of 16-bit words at adjacent memory address locations will be
accessed.
Note that the addressing for all Enhanced Mini-ACE pointers is
word-oriented, while all PCI addressing is byte-oriented. That is,
the value of a pointer stored in Enhanced Mini-ACE RAM will be
half of the value of the PCI address offset from the base memory
address for the particular Enhanced Mini-ACE. If not using the
Enhanced Mini-ACE API Library and you would like more informa-
tion about the Enhanced Mini-ACE registers and memory address-
es please reference the Enhanced Mini-ACE User’s Guide.
When using the API library provided with your card, the
Enhanced Mini-ACE registers and memory accesses are
abstracted from the end user to provide an easy-to-use High
Level C programming environment.
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