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參數(shù)資料
| 型號： | BU21018MWV |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, QCC56 |
| 封裝： | 7 X 7 MM, UQFN-56 |
| 文件頁數(shù)： | 2/5頁 |
| 文件大小： | 156K |
| 代理商： | BU21018MWV |
2/4
REV. C
●Electrical characteristics
PARAMETER
SYMBOL
RATING
UNIT
CONDITION
MIN
TYP
MAX
Digital Low level input
voltage
VIL1
-0.4
-
0.25*DVDD
V
Digital High level input
voltage
VIH1
0.7*DVDD
-
DVDD+0.5
V
Digital Low level output
voltage
VOL1
-
VSS+0.4
V
I
OL=2.0[mA]
Analog Low level output
voltage
VOL2
-
VSS+0.45
V
I
OL=1.0[mA]
Analog High level output
voltage
VOH2
LDO-0.4
-
LDO+0.5
V
I
OH=-0.5[mA]
OSC Frequency
Freq
21.0
24.0
27.0
MHz
Digital standby current
Ist1
0
-
10
uA
Analog standby current
Ist2
0
-
10
uA
Digital operating current
Idd1
-
3
5.5
mA
Analog operation current
Idd2
-
1
1.5
mA
*Ta = 25℃ as long as it doesn't specify it.
●Block diagram
CPU Core
Program
Memory
16kB
Data
Memory
2kB
CV
Transfer
Controller
Noise Filter
Clock
Controller
11
12
13
20
50
51
52
SIN00
SIN01
SIN02
SIN03
SIN33
SIN34
SIN35
RESET
(POR)
Calibration
Controller
EEPROM
I2C
1
10
I2C
5
6
Register
OSC
4
8
7
ADR_SEL
SCL
SDA
EDA
ECL
RESET
EXT_CLK
CPU Core
Program
Memory
16kB
Data
Memory
2kB
CV
Transfer
Controller
Noise Filter
Clock
Controller
11
12
13
20
50
51
52
SIN00
SIN01
SIN02
SIN03
SIN33
SIN34
SIN35
RESET
(POR)
Calibration
Controller
EEPROM
I2C
1
10
I2C
5
6
Register
OSC
4
8
7
ADR_SEL
SCL
SDA
EDA
ECL
RESET
EXT_CLK
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