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參數(shù)資料
| 型號： | BU3076HFV-TR |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 67.5 MHz, OTHER CLOCK GENERATOR, PDSO6 |
| 封裝： | ROHS COMPLIANT, HVSOF-6 |
| 文件頁數(shù)： | 8/21頁 |
| 文件大?。?/td> | 1528K |
| 代理商： | BU3076HFV-TR |
16/20
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Application circuit example
（
BU3071HFV）
（
BU3072HFV）
（
BU3073HFV）
（
BU3076HFV）
（
BU7322HFV）
（
BU7325HFV）
For VDD and VSS, insert a bypass capacitor of approx. 0.1 F as close as possible to the pin.
Bypass capacitors with good high-frequency characteristics are recommended.
Even though we believe that the typical application circuit is worth of a recommendation, please be sure to thoroughly
recheck the characteristics before use.
H:enable
L:disable
1：VDD
2：VSS
3：OUT
6：
IN
5：
TEST
4：
OE
28.6363MHz
54.0000MHz
H:enable
L:Hi-Z
H:36.0000MHz
L:27.0000MHz
1：VDD
2：VSS
3：OUT
6：IN
5：SEL
4：PD
H:36.0000MHz
L:27.0000MHz
48MHz
H:enable
L:disable
H:24.5454MHz
L:24.3750MHz
1：VDD
2：VSS
3：OUT
6：IN
5：SEL
4：PD
H:24.5454MHz
L:24.3750MHz
48MHz
Fig.101
Fig.102
Fig.103
Fig.104
Fig.105
Fig.106
H:enable
L:disable
H:67.5000MHz
L:54.0000MHz
1:VDD
2: VSS
3: OUT
6: IN
5: SEL
4: OE
H:67.5000MHz
L:54.00000MHz
27MHz
H:enable
L:disable
H:36.0000MHz
L:49.5000MHz
1:VDD
2: VSS
3: OUT
6: IN
5: SEL
4: OE
H:36.0000MHz
L:49.5000MHz
27MHz
H:enable
L:disable
H:78.0000MHz
L:48.0000MHz
1:VDD
2: VSS
3: OUT
6: IN
5: SEL
4: OE
H:78.0000MHz
L:48.0000MHz
27MHz
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