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參數(shù)資料
| 型號(hào)： | BU7331EKN-E2 |
| 廠商： | Rohm Semiconductor |
| 文件頁(yè)數(shù)： | 15/15頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN 3CH PLL 20HQFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時(shí)鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 頻率 - 最大： | 75MHz |
| 除法器/乘法器： | 無(wú)/無(wú) |
| 電源電壓： | 1.65 V ~ 1.95 V |
| 工作溫度： | -20°C ~ 75°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-QFN |
| 供應(yīng)商設(shè)備封裝： | 20-HQFN |
| 包裝： | 帶卷 (TR) |
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1995 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74LCX04
—
Lo
w
V
olta
g
e
He
x
In
ver
ter
with
5V
T
olerant
Inputs
Physical Dimensions
Figure 3. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specications do not expand the terms of Fairchild’s worldwide terms and conditions,
specically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
LAND PATTERN RECOMMENDATION
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
PIN ONE
INDICATOR
8
°
0
°
SEATING PLANE
DETAIL A
SCALE: 20:1
GAGE PLANE
0.25
X45
°
1
0.10
C
B
C
A
7
M
14
B
A
8
SEE DETAIL A
5.60
0.65
1.70
1.27
8.75
8.50
7.62
6.00
4.00
3.80
(0.33)
1.27
0.51
0.35
1.75 MAX
1.50
1.25
0.25
0.10
0.25
0.19
(1.04)
0.90
0.50
0.36
R0.10
0.50
0.25
74LCX04 Rev. 1.6.1
9
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