參數(shù)資料
型號(hào): BUF08821AIPWPR
廠商: TEXAS INSTRUMENTS INC
元件分類(lèi): 時(shí)鐘產(chǎn)生/分配
英文描述: VIDEO CLOCK GENERATOR, PDSO20
封裝: GREEN, PLASTIC, HTSSOP-20
文件頁(yè)數(shù): 4/27頁(yè)
文件大?。?/td> 654K
代理商: BUF08821AIPWPR
SBOS438C – AUGUST 2008 – REVISED AUGUST 2009 ................................................................................................................................................. www.ti.com
The process of updating multiple DAC/VCOM registers
3. Send the DAC/VCOM/OTHER pointer address
begins the same as when updating a single register.
byte. Set bit D7 = 0 and D6 = 0; bits D5–D0 are
However, instead of sending a STOP condition after
the DAC/VCOM/OTHER address. The BUF08821
writing the addressed register, the master continues
acknowledges, stores, and returns data only from
to send data for the next register. The BUF08821
these addresses:
automatically
and
sequentially
steps
through
000000 through 000111
subsequent registers as additional data are sent. The
010010
process continues until all desired registers have
111100 through 111111
been updated or a STOP or START condition is sent.
See
for
valid
DAC/VCOM/OTHER
To write to multiple DAC/VCOM registers:
addresses.
1. Send a START condition on the bus.
4. Send a START or STOP/START condition.
2. Send the device address and read/write bit =
5. Send the correct device address and read/write
LOW. The BUF08821 acknowledges this byte.
bit = HIGH. The BUF08821 acknowledges this
byte.
3. Send either the OUT1 pointer address byte to
start at the first DAC, or send the pointer address
6. Receive two bytes of data. They are for the
byte for whichever DAC/VCOM is the first in the
specified register. The most significant byte (bits
sequence of DACs/VCOM to be updated. The
D15–D8) is received first; next is the least
BUF08821 begins with this DAC/VCOM and steps
significant byte (bits D7–D0). In the case of
through subsequent DACs/VCOM in sequential
DAC/VCOM channels, bits D15–D10 have no
order.
meaning.
4. Send the bytes of data; begin by sending the
7. Acknowledge after receiving the first byte.
most significant byte (bits D15–D8, of which only
8. Send a STOP or START condition on the bus or
bits D9 and D8 have meaning, and bits D15–D14
do not acknowledge the second byte to end the
must not be 01), followed by the least significant
read transaction.
byte (bits D7–D0). The first two bytes are for the
Communication may be terminated by sending a
DAC/VCOM addressed in the previous step. The
premature STOP or START condition on the bus, or
DAC/VCOM register is automatically updated after
by not acknowledging.
receiving the second byte. The next two bytes are
for the following DAC/VCOM. That DAC/VCOM
To read multiple registers:
register is updated after receiving the fourth byte.
1. Send a START condition on the bus.
This process continues until the registers of all
following DACs/VCOM have been updated. The
2. Send the device address and read/write bit =
BUF08821 will continue to accept data for a total
LOW. The BUF08821 acknowledges this byte.
of 18 DACs; however, the ten data sets following
3. Send either the OUT1 pointer address byte to
the 8th data set will be meaningless. The 19th
start at the first DAC, or send the pointer address
data set will apply to VCOM. The write disable bit
byte for whichever register is the first in the
cannot be accessed using this method. It must be
sequence
of
DACs/VCOM to be read. The
written to using the write to a single DAC register
BUF08821 begins with this DAC/VCOM and steps
procedure.
through subsequent DACs/VCOM in sequential
5. Send a STOP or START condition on the bus.
order.
4. Send a START or STOP/START condition on the
The
BUF08821
acknowledges
each
byte.
To
bus.
terminate communication, send a STOP or START
condition on the bus. Only DAC registers that have
5. Send the correct device address and read/write
received both bytes of data are updated.
bit = HIGH. The BUF08821 acknowledges this
byte.
Reading: DAC/VCOM/OTHER Register (Volatile
6. Receive two bytes of data. They are for the
Memory)
specified DAC/VCOM. The first received byte is the
most significant byte (bits D15–D8, only bits D9
Reading a register returns the data stored in that
and
D8
have
meaning),
next
is
the
least
DAC/VCOM/OTHER register.
significant byte (bits D7–D0).
To read a single DAC/VCOM/OTHER register:
7. Acknowledge after receiving each byte of data.
1. Send a START condition on the bus.
8. When all desired DACs have been read, send a
2. Send the device address and read/write bit =
STOP or START condition on the bus.
LOW. The BUF08821 acknowledges this byte.
12
Copyright 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): BUF08821
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