參數(shù)資料
型號: BUK110-50GL
廠商: NXP SEMICONDUCTORS
元件分類: 外設(shè)及接口
英文描述: PowerMOS transistor Logic level TOPFET
中文描述: BUF OR INV BASED PRPHL DRVR, PSSO3
封裝: SOT404, 3 PIN
文件頁數(shù): 9/11頁
文件大?。?/td> 109K
代理商: BUK110-50GL
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK110-50GL
Fig.26. Normalised limiting clamping energy.
E
DSM
% = f(T
mb
); conditions: I
D
= 25 A; V
IS
= 10 V
Fig.27. Clamping energy test circuit, R
IS
= 50
.
E
DSM
=
0.5
LI
D
Fig.28. Typical off-state leakage current.
I
DSS
= f(T
j
); Conditions: V
DS
= 40 V; I
IS
= 0 V.
Fig.29. Normalised input current (normal operation).
I
IS
/I
IS
25 C = f(T
j
); V
IS
= 5 V
Fig.30. Normalised input current (protection latched).
I
ISL
/I
ISL
25 C = f(T
j
); V
IS
= 5 V
0
20
40
60
80
100
120
140
Tmb / C
EDSM%
120
110
100
90
80
70
60
50
40
30
20
10
0
-60
-20
20
60
Tj / C
100
140
180
Iiso normalised to 25 C
1.5
1
0.5
L
D.U.T.
VDD
RIS
R 01
shunt
VDS
-ID/100
+
-
VIS
0
P
D
S
I
TOPFET
ID
0
VDS
0
VDD
V(CL)DSS
Schottky
-60
-20
20
60
Tj / C
100
140
180
Iisl normalised to 25 C
1.5
1
0.5
2
V
(
CL
)
DSS
/(
V
(
CL
)
DSS
V
DD
)
0
20
40
60
80
100
120
140
Tj / C
Idss
1 mA
100 uA
10 uA
1 uA
100 nA
typ.
June 1996
9
Rev 1.000
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