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參數(shù)資料
| 型號(hào)： | BUS-63106-360Z |
| 英文描述： | FPGA (Field-Programmable Gate Array) |
| 中文描述： | 總線收發(fā)器 |
| 文件頁(yè)數(shù)： | 2/4頁(yè) |
| 文件大?。?/td> | 49K |
| 代理商： | BUS-63106-360Z |
2
ORDERING INFORMATION
BUS-615XX- XX0X
Supplemental Process Requirements:
S = Pre-Cap Source Inspection
L = Pull Test
Q = Pull Test and Pre-Cap Inspection
K = One Lot Date Code
W = One Lot Date Code and PreCap Source
Y = One Lot Date Code and 100% Pull Test
Z = One Lot Date Code, PreCap Source and 100% Pull Test
Blank = None of the Above
Process Requirements:
0 = Standard DDC Processing, no Burn-In (See Page 13.)
1 = MIL-PRF-38534 Compliant
2 = B*
3 = MIL-PRF-38534 Compliant with PIND Testing
4 = MIL-PRF-38534 Compliant with Solder Dip
5 = MIL-PRF-38534 Compliant with PIND Testing and Solder Dip
6 = B* with PIND Testing
7 = B* with Solder Dip
8 = B* with PIND Testing and Solder Dip
9 = Standard DDC Processing with Solder Dip, no Burn-In (See Page 13.)
Temperature Grade/Data Requirements:
1 = -55°C to +125°C
2 = -40°C to +85°C
3 = 0°C to +70°C
4 = -55°C to +125°C with Variables Test Data
5 = -40°C to +85°C with Variables Test Data
8 = 0°C to +70°C with Variables Test Data
Power Supply
3 = -15 V Transceivers
4 = -12 V Transceivers
5 = +5 V Transceivers–Call Factory
6 = Transceivers–Use with BUS-63102II–Call Factory
Packaging
5 = DDIP
6 = Flat Pack
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BUS-63106-370 | FPGA (Field-Programmable Gate Array) |
| BUS-63106-370K | FPGA (Field-Programmable Gate Array) |
| BUS-63106-370L | IC APEX 20KE FPGA 100K 208-PQFP |
| BUS-63106-370Q | IC APEX 20KE FPGA 100K 240-PQFP |
| BUS-63106-370S | IC APEX 20KE FPGA 100K 240-PQFP |
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