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參數(shù)資料
| 型號(hào)： | BW1221L |
| 英文描述： | Rad hard low voltage CMOS 16-bit bus buffer transceiver (3-state) with 3.6 V tolerant inputs and outputs |
| 中文描述： | BW1221L 10位80Msps的雙DAC BW1221L |數(shù)據(jù)資料 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 140K |
| 代理商： | BW1221L |
BW1223X
8BIT 40MSPS ADC
SEC ASIC
ANALOG
FUNCTIONAL
DESCRIPTION
1.
BW1223X
converter
matrix.
It consists of 4-bit coarse A/D converter and fine
A/D converter of which the accuracy is 4.459
bits. The latching comparators in coarse and fine
A/D converters have offset cancellation features
built in such as auto-zero and averaging, and the
number of comparators are 15 in the coarse
converter and 42 in the fine one.
The sampling operation of fine A/D converter is
performed,
through
21
ping-pong
manner
between
amplifier banks each of which consists of 21
latching comparators.
is
a
two-step
ping-pong
reference
A/D
with
subranging
resistor
analog
MUXs,
two sampling
in
a
the
2. The reference resistor matrix switch one of the
16 different sets of reference voltages, according
to the states of the coarse comparator digital
outputs, to the fine sampling amplifier banks.
This fact and the use of a CMOS auto-zero
comparator surely eliminate the extra pain for
implementing high accuracy D/A converter of 8
bits
or
more,
and
high-performance and high speed A/D converter
results.
thus
a
low-power,
3. The operation of BW1223X can be stated as
follows. (refer to the 'TIMING DIAGRAM' that
follows)
During the first cycle of external clock, the
analog input 'AIN' is traced by each converter,
and at the falling edge of CLK the 'AIN' is
sampled and held to be compared with the
16-level coarse reference voltages. The result of
comparison
in
coarse
latched and used to select a set of fine reference
voltage 'FREF' which, to be compared with the
sampled analog input, is fed to the fine sampling
amplifier banks. The result of the comparison is
reproduced
by
successive
sufficiently large gain and then multiplexed to
the latching digital logic in a ping-pong manner.
Latching logic in coarse and fine converters
refine the results of comparison to generate A/D
comparator,
'COUT',
is
comparators
with
converter output 'FOUT' and 'COUT',
which the final digital output 'DO' is generated.
The overall pipeline delay, measured from the
sampling instance to the time that the 'DO'
comes to be available, is 2.5 clock cycles.
and from
4.
BW1223X
scheme to correct the error which stems from
the mismatch between the offset of coarse A/D
converter and that of the fine A/D converter.
This scheme can handle coarse comparator offset
error up to 3 LSBs and helps reducing the
differential linearity error consequently.
implements
the
error
correction
6 / 11
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BW1221L_2CLK | Rad hard low voltage CMOS 16-bit bus buffer transceiver (3-state) with 3.6 V tolerant inputs and outputs |
| BW1221L_3CLK | Rad hard low voltage CMOS 16-bit bus buffer transceiver (3-state) with 3.6 V tolerant inputs and outputs |
| BW1222L | Rad hard low voltage CMOS 16-bit D-type latch (3-state) with 3.6 V tolerant inputs and outputs |
| BW1237X | Rad hard low voltage CMOS 16-bit D-type Flip-Flop (3-state) with 3.6 V tolerant inputs and outputs |
| BW1238X | Rad hard low voltage CMOS 16-bit D-type Flip-Flop (3-state) with 3.6 V tolerant inputs and outputs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BW1221L_2CLK | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BW1221L_2CLK 10BIT|Data Sheet |
| BW1221L_3CLK | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BW1221L_3CLK 10Bit 30MSPS TRIPLE DAC|Data Sheet |
| BW1222L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BW1222L AFE For CCD/CIS Signal Processor|Data Sheet |
| BW1223X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BW1223X 8Bit 40MSPS ADC BW1223X|Data Sheet |
| BW1224L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BW1224L AFE for CCD/CIS Signal Processor BW1224L|Data Sheet |
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